pt7a6525 Pericom Technology Inc, pt7a6525 Datasheet - Page 12

• Manufacturer Part Number: pt7a6525
• Description: Pt7a6525/6525l/6526 Hdlc Controller
• Manufacturer: Pericom Technology Inc

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Modes of Operation
There are 6 different modes of operation that can be set via the
MODE register. The treatment of received frames and those
that are waiting for transmission is determined by the selected
modes of operation.
Auto Mode (MODE: MDS1, MDS0 = 00)
Characteristics: Window size 1, arbitrary message length,
address recognition.
The PT7A6526 processes automatically all numbered frames
(S, I frames) of an HDLC procedure.
The HDLC control field, data in the I field of the frames, and
additional information can be read from special registers (RHCR,
RSTA).
According to the selected Address Mode, the device can
perform 2-byte or 1-byte address recognition. If a 2-byte address
field is selected, the high address byte is compared with the
fixed value FEH or FCH (group address) as well as with two
individually programmable values in the RAH1 and RAH2
registers. In accordance with the ISDN LAPD protocol, bit 1 of
the high address byte is interpreted as COMMAND/
RESPONSE bit (C/R) depending upon the setting of the CRI bit
in RAH1 and will be excluded from the address comparison.
Similarly, two reference values can be programmed in special
registers (RAL1, RAL2) for the low address byte. A valid address
will be recognized if the high and low byte of the address field
correspond to one of the reference values. Thus, the device
can be addressed (called) with six different address
combinations. However, only those frames whose addresses
match with the address combination RAH1, RAL1 are processed
in Auto Mode; all others are processed in Non-auto Mode.
The PT7A6526 ignores such HDLC frames whose address fields
do not match with any of the address combinations.
For the 1-byte address case, the RAL1 and RAL2 registers are
used as reference. In accordance with the X.25 LAPB protocol,
the value in RAL1 is interpreted as COMMAND and the value
in RAL2 as RESPONSE.
After receiving a frame it takes 5 clock cycles to generate the
response frame and to initiate transmission.
When operating in Auto Mode, the device provides substantial
procedural support.
PT0017(12/05)
12
PT7A6525/6525L/6526 HDLC Controller
The following functions are performed:
In addition, all unnumbered frames are forwarded directly to the
microprocessor.
Non-Auto Mode (MODE: MDS1, MDS0 = 01)
Characteristics: address recognition, arbitrary window size.
All frames with valid addresses (address recognition identical
to Auto Mode) are forwarded directly to the system memory.
The HDLC control field, data in the I field, and an additional
status byte are temporarily stored in the RFIFO. The HDLC
control field and additional information can also be read from
special registers (RHCR, RSTA).
In Non-Auto Mode, all frames are processed similarly as in
Auto Mode.
Transparent Mode 1 (MODE: MDS1, MDS0, ADM = 101)
Characteristics: high address byte recognition
Only the high byte of a 2-byte address field will be compared
with the reference values. The entire frame, except for the first
address byte, will be stored in RFIFO. RAL1 contains the second
byte, and RHCR the third byte following the opening flag.
Transparent Mode 0 (MODE: MDS1, MDS0, ADM = 100)
Characteristics: no address recognition
There is no address recognition process performed, and each
frame will be stored in the RFIFO. RAL1 contains the first byte,
and RHCR the second byte following the opening flag.
Extended Transparent Mode 0 and Mode 1 (MODE: MDS1,
MDS0 = 11)
Characteristics: fully transparent
- updating transmit and receive counter ,
- evaluation of transmit and receive counter,
- processing S commands,
- flow control with RR/RNR,
- generation of responses,
- recognition of protocol errors,
- transmitting S commands (if acknowledgement is
- continuous status query of opposite station
- programmable timer/repeater functions.
missing),
after RNR has been received,
Data Sheet
,
s termination
Ver:8