pt7a6525 Pericom Technology Inc, pt7a6525 Datasheet - Page 29

• Manufacturer Part Number: pt7a6525
• Description: Pt7a6525/6525l/6526 Hdlc Controller
• Manufacturer: Pericom Technology Inc

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Operational Description
Reset
The PT7A6526 is forced into the Reset state if HIGH level is
input to the RES pin for at least 1.8ms. During RESET, the device
is temporarily in the power-up mode, and a subset of the registers
is initialized with defined values.
After Reset, the device is in power-down mode. The defined
values for the registers are shown in Table 8.
Initialization
After Reset, the microprocessor must write to a minimum set of
registers, plus an optional set, depending on the required
features and modes of operation.
First, the serial port configuration and the clock mode need to
be defined via the CCR1 register. The clock mode must be set
before power-up, or simultaneously with power-up.
The microprocessor may switch the device between power-up
and power-down modes with no influence upon the contents
of the registers; the internal state remains unchanged.
In power-down state, however, all internal clocks and oscillator
circuitry are disabled; no interrupts are forwarded to the
microprocessor.
This state can be used as standby mode when the device is
temporarily not needed, thus greatly reducing the power
consumption.
After initialization, the microprocessor switches each individual
channel of the PT7A6526 into operational phase by setting the
PU bit in the CCR1 register (power-up, if not already done during
initialization).
Initially, the microprocessor should bring the transmitter and
receiver to a defined state by issuing a XRES (transmitter reset)
and RHR (receiver reset) command via the CMDR register. If
data reception will be performed, the receiver must be activated
by setting the RAC bit in MODE to 1.
PT0017(12/05)
29
PT7A6525/6525L/6526 HDLC Controller
If no Clear to Send function is provided via a modem, the CTS
pin must be connected directly to ground in order to enable
data transmission.
Now the device is ready to transmit and receive data. Control of
the data transfer phase is performed mainly by commands from
microprocessor to device via the CMDR register, and by interrupt
indications from device to microprocessor.
Additional status information (which does not trigger interrupts)
is available in the STAR register.
Data Transmission
• Interrupt Mode
In the transmit direction, 2x32 byte FIFO buffers (transmit pools)
are provided for each channel. After checking the XFIFO status
by polling the Transmit FIFO Write Enable bit (XFW in STAR
register), or after a Transmit Pool Ready (XPR) interrupt, up to
32 bytes may be sent by the microprocessor to the XFIFO.
The transmission of a frame can be started by issuing an XTF
or XIF command via the CMDR register. If the transmit command
does not include an End of Message indication (CMDR: XME),
the device will repeatedly request the next data block using an
XPR interrupt, as long as no more than 32 bytes are stored in
the XFIFO, i.e., a 32-byte pool is accessible to the
microprocessor.
This cycle will be repeated until the microprocessor indicates
the end of message command, after which frame transmission is
completed appropriately by appending the CRC and closing
flag sequence.
Whenever no more data is available in the XFIFO prior to the
arrival of XME, the transmission of the frame is terminated with
an abort sequence, and the microprocessor is notified per
interrupt (EXIR: XDU). The frame may also be terminated by
software (CMDR: XRES).
Data Sheet
Ver:8