pt7a6525 Pericom Technology Inc, pt7a6525 Datasheet - Page 24

• Manufacturer Part Number: pt7a6525
• Description: Pt7a6525/6525l/6526 Hdlc Controller
• Manufacturer: Pericom Technology Inc

| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
RTS Signal in Clock Mode 5
In Clock Mode 5, the Request to Send (RTS) control signal is
deactivated after transmission of the second-to-last bit (instead
of the last bit) of a closing flag, if that second-to-last bit is the
last bit of a time-slot “window”. In other words, RTS is inactive
during transmission of the last bit of any closing flag transmitted
in the next time-slot window.
CTS Signal in Clock Mode 5
In Clock Mode 5 the Clear to Send (CTS) control signal is
PT0017(12/05)
Figure 11. RTS Signal in Clock Mode 5
Figure 12. CTS Signal in Clock Mode 5
TxCLK
TxCLK
TxD
RTS
INT
TxD
RTS
CTS
DDD… D
Time-slot n
D
Time-slot n+1
24
PT7A6525/6525L/6526 HDLC Controller
evaluated not only within the time-slot window, but also
between the time-slot window CTS must be kept active even
between the time-slot window until transmission of the frame
has been completed. Deactivation of CTS stops data
transmission immediately.
Note: When several HDLC channels are sharing the same time-
slot on a bus without using Bus Collision Detection, the strobe
signals (AxCLKA/B) can be used to select/deselect a particular
time-slot window for an individual HDLC channel.
Last Bit of a Frame
IDLE, Interframe Time-fill
D = Valid Data Bits
Sampling
Data Sheet
Ver:8