pt7a6525 Pericom Technology Inc, pt7a6525 Datasheet - Page 13

• Manufacturer Part Number: pt7a6525
• Description: Pt7a6525/6525l/6526 Hdlc Controller
• Manufacturer: Pericom Technology Inc

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In Extended Transparent Modes, the fully transparent data
transmission/reception process without HDLC framing is
performed, i.e., without FLAG generation/recognition, CRC
generation/check, and bit-stuffing/removal. This allows user
specific protocol variations or the usage of Character Oriented
Protocols (such as IBM BISYNC).
In these modes, the transmitted data always passes through
the XFIFO. In Extended Transparent Mode 0 (ADM = 0), data
reception is done via the RAL1 register, which always contains
the actual data byte assembled at the RxD pin. In Extended
Transparent Mode 1 (ADM = 1), the received data is also shifted
into the RFIFO.
In order to enable fully transparent data transfer, the RAC bit in
MODE must be reset, and FFH has to be written to XAD1,
XAD2, and RAH2.
Data transmission is always performed out of the transmit FIFO
by directly shifting the contents of the XFIFO via the serial
PT0017(12/05)
Table 3. HDLC Frames in Various Operation Modes
Note: RFIFO: Receive FIFO
T
T
N
N
a r
a r
n o
n o
A
s n
A
s n
M e d
M
M
M
M
u
A -
A -
RHCR: Receive HDLC Control Register
RSTA: Receive Status Register
RAL1,2: Receive Address Low1,2
RAH1,2: Receive Address High1,2
u
a p
a p
/ o t
o
o
o
o
o
o t
u
e d
e d
e d
e d
u
e r
e r
8 /
/ o t
6 1
o t
t n
t n
6 1
8 /
0
1
M
M
M
M
M
D
D
D
D
D
0
0
0
0
1
1
1 S
1 S
1 S
1 S
1 S
M
M
M
M
M
D
D
D
D
D
0
0
0
0
1
1
0 S
0 S
0 S
0 S
0 S
A M
A M
A M
A M
A
D
D
D
D
D
0
0
0
1
1
1
M
∆
∆
∆
∆
∆
A
R
R
R
R
R
d
R
R
F
A
r d
A
A
A
A
A
F I
L
s e
H
H
H
L
L
O
* 1
13
PT7A6525/6525L/6526 HDLC Controller
1
1
1
1
1
2 s
*
2 ,
2 ,
2 ,
2 ,
2 ,
transmit data pin (TxD). Transmission is initiated by setting
CMDR: XTF (08H); end of transmission is indicated by EXIR:
EXE (40H). In the receive direction, the data currently assembled
via the receive data line (RxD) is available in the RAL1 register.
Additionally, in Extended Transparent Mode 1 (MODE: MDS1,
MDS0, ADM = 111), the received data is shifted into the RFIFO.
If the Extended Transparent Modes are selected, the device
supports the continuous transmission of the XFIFO
After having written 1 to 32 bytes to the XFIFO, the commands
XREP, XTF and XME (by writing 2AH to the CMDR register)
force the chip to repeatedly transmit the data stored in the
XFIFO via TxD pin, until a reset command (CMDR: XRES) is
issued, after which continuous 1 -s are transmitted.
Note: In DMA Mode the commands XREP and XTF must be
written to CMDR.
The management of received HDLC frames in various modes of
operation is shown in the following table:
D: Compared with Register
#: Processed Autonomously
*: Stored to FIFO or Register
- : the byte does not exist
∆
∆
A
R
R
R
R
R
d
R
F
F
H
A
r d
A
F I
F I
A
C
-
-
L
s e
L
L
O
O
R
* 1
1
1
1 s
*
*
*
2 ,
2 ,
R
R
R
R
R
e
e
e
e
e
e c
e c
e c
e c
e c
v i
v i
v i
v i
v i
d e
d e
d e
d e
d e
R
R
R
R
R
R
R
R
R
R
R
C
F
F
F
F
F
F
H
H
H
H
H
n o
P
P
P
P
P
F I
F I
F I
F I
F I
F I
#
#
C
C
C
C
C
c a
c a
c a
c a
c a
r t
O
R
O
R
O
R
O
R
O
R
O
l o
a k
a k
a k
a k
a k
*
*
*
*
*
*
*
*
*
*
*
e g
e g
e g
e g
e g
R
R
R
R
R
R
I
F
F
F
F
F
F
e i f
F I
F I
F I
F I
F I
F I
d l
O
O
O
O
O
O
Data Sheet
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,
R
R
R
R
R
R
s contents.
R
R
R
R
R
R
C
F
F
F
F
F
F
S
S
S
S
S
S
F I
F I
F I
F I
F I
F I
R
T
T
T
T
T
T
A
A
A
A
A
A
C
O
O
O
O
O
O
Ver:8
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