wm8350 Wolfson Microelectronics plc, wm8350 Datasheet - Page 62

• Manufacturer Part Number: wm8350
• Description: Wolfson Audioplus? Stereo Codec With Power Management
• Manufacturer: Wolfson Microelectronics plc

WM8350
13.3 ENABLING THE AUDIO CODEC
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Before the audio CODEC can be used, it must be enabled by writing to the CODEC_ENA,
SYSCLK_ENA and BIAS_ENA register bits.
ADDRESS
R12 (0Ch)
Power
Mgmt 5
R11 (0Bh)
Power
Mgmt 1
R8 (08h)
Power
Mgmt 1
Table 19 Enabling the Audio CODEC
Each individual part of the audio CODEC (e.g. left/right ADC, left/right DAC, each analogue output
pin, mic bias etc.) also has its own enable bit, which must be set before that part of the CODEC can
be used. These enable bits are described in the sections that follow.
In order to minimize output pop and click noise, it is recommended that the WM8350 device is
powered up and down under control using the following sequences:
Power Up:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Ensure the CODEC power supplies are available before the CODEC is enabled
(CODEC_ENA = 1). The order in which this is done should be DCVDD, DBVDD then HPVDD
And/Or AVDD
Mute all outputs
Enable the anti-pop circuits by setting ANTI_POP. There are three Anti-pop setting options.
Recommended value is ANTI_POP = 01.
Ensure external capacitors are fully discharged on all outputs that are used by delaying 250ms
Set the mixers and DAC volume to required settings
Enable VMID by setting VMID_ENA = 1. VMID should raise in a controlled fashion and charge
the output capacitors
Wait approx 500ms to allow VMID to charge.
Disable the anti-pop circuits by setting ANTI_POP = 00.
Un-mute all outputs
BIT
12
14
5
CODEC_ENA
SYSCLK_ENA
BIAS_ENA
LABEL
DEFAULT
0
0
0
Master codec enable bit. Until this bit is set, all
codec registers are held in reset.
0 = All codec registers held in reset
1 = Codec registers operate normally.
CODEC SYSCLK enable
0 = disabled
1 = enabled
Enables bias to analogue audio CODEC
circuitry
0 = disabled
1 = enabled
DESCRIPTION
PD, June 2009, Rev 4.1
Production Data
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