wm8805 Wolfson Microelectronics plc, wm8805 Datasheet - Page 13

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wm8805

Manufacturer Part Number
wm8805
Description
8 1 Digital Interface Transceiver With Pll
Manufacturer
Wolfson Microelectronics plc
Datasheet

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When the device powers up, all power up configuration pins are configured as inputs for a minimum
of 9.4us and a maximum of 25.6us following the release of the external reset. The times are based
on 27MHz and 10MHz crystal clock frequencies respectively. This enables the pins to be sampled
and the device to be configured before the pins are released to their selected operating conditions.
Figure 7 illustrates how SDIN is sampled.
Figure 7 Pin Sampling On Power Up or Hardware Reset
If the device is powered up in Software control mode, all functions of the device are powered down by
default and must be powered up individually by writing to the relevant bits of the PWRDN register
(Table 7). In Hardware Control Mode, all functions of the device are powered up by default.
Table 7 Power Down Register
REGISTER ADDRESS
RSTB
SDIN
PWRDN
R30
1Eh
Sampling of pin value at reset to
On Reset
generate internal signals.
Power-
BIT
2
4
0
1
3
5
SPDIFTXPD
SPDIFRXP
POR_B
OSCPD
LABEL
AIFPD
PLLPD
TRIOP
D
DEFAULT
D
ENB
1
0
1
1
0
0
Q
PLL Powerdown
0 = PLL enabled
1 = PLL disabled
S/PDIF Receiver Powerdown
0 = S/PDIF receiver enabled
1 = S/PDIF receiver disabled
S/PDIF Transmitter
Powerdown
0 = S/PDIF transmitter enabled
1 = S/PDIF transmitter disabled
Oscillator Power Down
0 = Power Up
1 = Power Down
Digital Audio Interface Power
Down
0 = Power Up
1= Power Down
Tri-state all Outputs
0 = Outputs not tri-stated
1 = Outputs tri-stated
HWMODE
SWMODE
DESCRIPTION
PD, Rev 4.5, March 2009
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WM8805
13

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