wm8805 Wolfson Microelectronics plc, wm8805 Datasheet - Page 26

• Manufacturer Part Number: wm8805
• Description: 8 1 Digital Interface Transceiver With Pll
• Manufacturer: Wolfson Microelectronics plc

WM8805
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Table 25 Audio Interface Mode Select
When MCLK is configured as an output, the MCLK source and rate can be selected using the control
bits shown in Table 26. The MCLK rate select can only be used when the MCLK output source is
selected as the PLL clock. If the oscillator clock is selected as the PLL source, the MCLK frequency
is equal to the oscillator clock frequency.
Table 28 PLL S/PDIF Receive Mode Clock Divider Configuration
Note: The fs values shown above are relative to the S/PDIF recovered sample rate.
When MCLK is configured as an input, the reference clock rate for the S/PDIF transmitter (when the
digital audio interface received data is configured as the S/PDIF transmitter data source) is controlled
by the frequency of the MCLK signal at the MCLK pin.
Refer to the “Digital Audio Interface” datasheet section for details of configuring MCLK for appropriate
digital audio interface operation.
CLOCK OUTPUT (CLKOUT)
The high-drive clock output (CLKOUT) pin can be used as a clock output. This pin is intended to be
used as a clock source pin for providing the central clock reference for an audio system.
The CLKOUT clock source can be selected from either the OSCCLK or CLK1 signals. The control
bits for the CLKOUT signal are shown in Table 29.
Table 26 Master Clock Output Control
Table 27 PLL User Mode Clock Divider Configuration
CLKOUTDIV[1:0]
FREQMODE[1:0]
REGISTER
REGISTER
ADDRESS
ADDRESS
AIFRX
PLL5
PLL6
R28
1Ch
07h
08h
R7
R8
00
01
10
11
00
01
10
11
BIT
BIT
6
3
7
00
÷2
÷2
÷4
÷6
CLK1 FREQUENCY
F
2
MCLKSRC
MCLKDIV
TO CLK1 DIVISION FACTOR
AIF_MS
LABEL
LABEL
512fs
256fs
128fs
CLKOUTDIV[1:0]
64fs
÷12
01
÷2
÷4
÷8
÷16
÷24
10
÷4
÷8
DEFAULT
DEFAULT
0
0
0
MCLKDIV
÷16
÷32
÷48
11
÷8
0
1
Audio Interface Mode Select
0 = Slave Mode – MCLK Input
1 = Master Mode – MCLK Output
MCLK Divider Select
(Only valid when CLK2 is selected
as MCLK output source)
See Table 27 for MCLKDIV
configuration in PLL user mode.
See Table 28 for MCLKDIV
configuration in PLL S/PDIF receive
mode.
MCLK Output Source Select
0 = Select CLK2
1 = Select OSCCLK
F
2
TO CLK2 DIVISION FACTOR
÷12
÷2
÷4
÷8
0
CLK2 FREQUENCY
DESCRIPTION
DESCRIPTION
PD, Rev 4.5, March 2009
MCLKDIV
256fs
128fs
Production Data
÷16
÷24
÷4
÷8
1
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