wm8805 Wolfson Microelectronics plc, wm8805 Datasheet - Page 29

• Manufacturer Part Number: wm8805
• Description: 8 1 Digital Interface Transceiver With Pll
• Manufacturer: Wolfson Microelectronics plc

w
Production Data
TO CONFIGURE THE SYSTEM WHEN CLOCKING MODE (SAMPLE RATE) CHANGES TO OR
FROM MODE 1 (176.4/192KHZ):
Any sample rate change between clocking modes (for example, from 44.1kHz (mode 3) to 192kHz
(mode 1)) will be flagged to the application processor via the INT_N interrupt flag. The application
processor must then read the Interrupt Status Register. If the UPD_REC_FREQ flag is set, indicating
that the clocking mode has changed, proceed as follows:
This procedure is only strictly necessary when switching to or from 192kHz (mode 1) because the
PLL_N and PLL_K values are the same for 32/44.1/48/88.2/96kHz (modes 2/3/4) sample rate
operation. It is, however, good interrupt service routine practice to write the appropriate PLL_N and
PLL_K values when every clocking mode change is detected. The setup for 176.4 kHz and 192kHz
are however slightly different. The setting up of these different configurations are described in the
following paragraphs.
176.4KHZ OR 192K MODE ENABLE
The difference between a sample rate of 176.4kHz and 192kHz requires the system to be configured
slightly differently. This requires that the S/PDIF Rx sample rates are known (176.4kHz or 192kHz).
Both sampling frequencies also require that the register bit SPD_192K_EN is set to a 1. If the
SPD_192K_EN register bit is not set to a 1, then TRANS_ERR errors will be generated and this will
result in the UNLOCK status being continually set (indicating an UNLOCK status).
176.4KHZ OPERATION
To operate at fs=176.4 kHz, then the PLL_K and PLL_N settings should be set up as in mode 2/3/4.
In this case the the PLL will lock onto the S/PDIF Rx data stream correctly if fs=176.4kHz. If however
the sample rate is changed to fs=192kHz (and the PLL is not reconfigured) then the S/PDIF Rx
interface will indicate UNLOCK and TRANS_ERR. The UNLOCK signal will continually toggle
between a locked and unlocked state.
192KHZ OPERATION
To operate at fs=192kHz, then the PLL_K and PLL_N settings should be set up as in mode 1. In this
case the the PLL will lock onto the S/PDIF Rx data stream correctly if fs=192kHz. If however the
sample rate is changed to fs=176.4kHz (and the PLL is not reconfigured) then the S/PDIF Rx
interface will indicate UNLOCK and TRANS_ERR. The UNLOCK signal will continually toggle
between a locked and unlocked state. Note that this is the default setting for hardware mode.
Table 32 176.4/192 kHz Sample Rate Enable
REGISTER
ADDRESS
SPDRX1
R29
1Dh
5.
1.
2.
If indicated sample rate is 192kHz, then the user must know what the sampling
frequency is (176.4kHz or 192kHz) since these cannot be distinguished. The user
should then write appropriate calculated values (relative to oscillator frequency) to
PRESCALE, PLL_N and PLL_K for 176.4/192kHz (mode 1) S/PDIF receiver sample
rate operation.
Read S/PDIF Status Register REC_FREQ[1:0] bits to identify recovered S/PDIF
sample rate frequency and clocking mode. If “192kHz” is indicated then since this is
indistinguishable from 176.4kHz, the user must be aware of what the sampling
frequency is.
Write appropriate calculated values (relative to oscillator frequency) to PLL_N and
PLL_K based on indicated recovered S/PDIF sample frequency and clocking mode.
BIT
7
SPD_192K_EN
LABEL
DEFAULT
1
S/PDIF Receiver 192kHz Support
Enable
0 = disabled, S/PDIF receiver
maximum supported sampling
frequency is 96kHz
1 = enabled, S/PDIF receiver
maximum supported sampling
frequency is 192kHz
DESCRIPTION
PD, Rev 4.5, March 2009
WM8805
29