zl2005 Intersil Corporation, zl2005 Datasheet - Page 19

• Manufacturer Part Number: zl2005
• Description: Digital-dc? Integrated Power Management And Conversion Ic
• Manufacturer: Intersil Corporation

Configuration A: SYNC OUTPUT
When the SYNC pin is configured as an output (CFG
pin is tied HIGH), the device will operate from its
internal oscillator and will drive the resulting internal
oscillator signal (preset to 400 kHz) onto the SYNC
pin so other devices can be synchronized to it. The
SYNC pin will not be checked for an incoming clock
signal while in this configuration.
Configuration B: SYNC INPUT
When the SYNC pin is configured as an input (CFG
pin is tied LOW), the device will automatically check
for a clock signal on the SYNC pin each time EN is
asserted. The ZL2005’s oscillator will then synchro-
nize with the rising edge of external clock.
The incoming clock signal must be in the range of 200
kHz to 2 MHz and must be stable when the enable pin
is asserted. The clock signal must also exhibit the nec-
essary performance requirements (see Table 3). In the
event of a loss of the external clock signal, the output
voltage may show transient over/undershoot.
If this happens, the ZL2005 will turn off the power
FETs (QH and QL in Figure 4) typically within 10 μS.
Users are discouraged from removing an external
SYNC clock while the ZL2005 is operating with
Enable asserted.
200 kHz – 2 MHz
200 kHz – 2 MHz
SYNC
19
ZL2005
N/C
A) SYNC = output
SYNC
Figure 12. SYNC Pin Configurations
ZL2005
Logic
high
OR
C) SYNC = Auto Detect
Open
Logic
Logic
ZL2005
high
low
SYNC
200 kHz – 2 MHz
Configuration C: SYNC AUTO DETECT
When the SYNC pin is configured in auto detect mode
(CFG pin is left OPEN), the device will automatically
check for a clock signal on the SYNC pin after enable
is asserted.
If a clock signal is present, The ZL2005’s oscillator
will then synchronize the rising edge of the external
clock. Refer to SYNC INPUT description.
If no incoming clock signal is present, the ZL2005 will
configure the switching frequency according to the
state of the SYNC pin as listed in Table 13. In this
mode, the ZL2005 will only read the SYNC pin con-
nection during the start-up sequence. Changes to
SYNC pin connections will not affect f
power (VDD) is cycled off and on.
Table 13. Switching Frequency Selection
If the user wishes to run the ZL2005 at a frequency
other than those listed in Table 13, the switching fre-
quency can be set using an external resistor, R
connected between SYNC and SGND using Table 14.
ZL2005
SYNC Pin Setting
N/C
Resistor
OPEN
HIGH
LOW
B) SYNC = input
SYNC
OR
ZL2005
R
SYNC
SYNC
ZL2005
See Table 14
Frequency
200 kHz
400 kHz
N/C
1 MHz
SW
February 18, 2009
until the
FN6848.0
SYNC
,