m52s128168a-7tig Elite Semiconductor Memory Technology Inc., m52s128168a-7tig Datasheet - Page 21

• Manufacturer Part Number: m52s128168a-7tig
• Description: 2m X 16 Bit X 4 Banks Synchronous Dram
• Manufacturer: Elite Semiconductor Memory Technology Inc.

ESMT
Burst Stop
(CLK). The burst stop command has the fewest restriction making it the easiest method to use when terminating a burst read
operation before it has been completed. When the burst stop command is issued during a burst read cycle, the pair of data and
DQS (Data Strobe) go to a high impedance state after a delay which is equal to the CAS latency set in the mode register. The burst
stop command, however, is not supported during a write burst operation.
1. The BST command may only be issued on the rising edge of the input clock, CLK.
2. BST is only a valid command during Read burst.
3. BST during a Write burst is undefined and shall not be used.
4. BST applies to all burst lengths.
5. BST is an undefined command during Read with autoprecharge and shall not be used.
6. When terminating a burst Read command, the BST command must be issued L
7. When the burst terminates, the DQ and DQS pins are tristated.
The BST command is not byte controllable and applies to all bits in the DQ data word and the (all) DQS pin(s).
Elite Semiconductor Memory Technology Inc.
The burst stop command is initiated by having RAS and CAS high with CS and WE low at the rising edge of the clock
The Burst Stop command is a mandatory feature for Mobile DDR SDRAM. The following functionality is required.
clock edge at which the output buffers are tristated, where L
C O M M A N D
D Q S
D Q ' s
C L K
C L K
<Burst Length = 4, CAS Latency = 3 >
R E A D A
0
H i - Z
H i - Z
Burst Stop
1
Preliminary
N O P
2
D out 0 Dout 1
N O P
BST
3
equals the CAS latency for read operations.
N O P
The burst read ends after a deley equal to the CAS lantency.
4
N O P
BST
5
( “BST Latency”) clock cycles before the
N O P
Revision : 1.4
Publication Date : Sep. 2008
6
N O P
M53D128168A
7
N O P
8
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