m52s128168a-7tig Elite Semiconductor Memory Technology Inc., m52s128168a-7tig Datasheet - Page 42

• Manufacturer Part Number: m52s128168a-7tig
• Description: 2m X 16 Bit X 4 Banks Synchronous Dram
• Manufacturer: Elite Semiconductor Memory Technology Inc.

ESMT
Deep Power Down Mode Entry & Exit Cycle
Note :
DEFINITION OF DEEP POWER MODE FOR Mobile DDR SDRAM :
Deep Power Down Mode is an operating mode to achieve maximum power reduction by cutting the power of the whole memory of
the device. Once the device enters in Deep Power Down Mode, data will not be retained. Full initialization is required when the
device exits from Deep Power Down Mode.
TO ENTER DEEP POWER DOWN MODE
1)
2)
3)
TO EXIT DEEP POWER DOWN MODE
4)
5)
6)
Elite Semiconductor Memory Technology Inc.
The deep power down mode is entered by having CS and held low with RAS and CAS high at the rising edge of the
clock. While CKE is low.
Clock must be stable before exited deep power down mode.
Device must be in the all banks idle state prior to entering Deep Power Down mode.
The deep power down mode is exited by asserting CKE high.
In case of 2/CS, 2CKE device with 2/CS & 2CKE, 200μs wait tine is required even if only 1 device exits from Deep Power
Down.
Upon exiting deep power down an all bank precharge command must be issued followed by two auto refresh commands
and a load mode register sequence.
Preliminary
Revision : 1.4
Publication Date : Sep. 2008
M53D128168A
42/47