m52s128168a-7tig Elite Semiconductor Memory Technology Inc., m52s128168a-7tig Datasheet - Page 24

• Manufacturer Part Number: m52s128168a-7tig
• Description: 2m X 16 Bit X 4 Banks Synchronous Dram
• Manufacturer: Elite Semiconductor Memory Technology Inc.

ESMT
Self Refresh
clock (CLK). Once the self refresh command is initiated, CKE must be held low to keep the device in self refresh mode. During the
self refresh operation, all inputs except CKE are ignored. The clock is internally disabled during self refresh operation to reduce
power consumption. The self refresh is exited by supplying stable clock input before returning CKE high, asserting deselect or NOP
command and then asserting CKE high for longer than t
Power Down
The device enters power down mode when CKE Low, and it exits when CKE High. Once the power down mode is initiated, all of
the receiver circuits except CLK and CKE are gated off to reduce power consumption. All banks should be in idle state prior to
entering the precharge power down mode and CKE should be set in high for at least t
operations cannot be performed during power down mode, therefore the device cannot remain in power down mode longer than
the refresh period(t
Elite Semiconductor Memory Technology Inc.
C O M M A N D
C O M M A N D
A self refresh command is defines by having CS , RAS , CAS and CKE held low with WE high at the rising edge of the
C L K
C L K
C K E
C K E
C L K
C L K
Precharge
N O P
REF
) of the device.
t
Ref resh
I S
Self
E n t e r P re c h a rg e
p o w e r- d o wn
t
IS
m o d e
Preliminary
XSRD
for locking of DLL.
N O P
E n t e r P r e c h a r g e
p o w e r -d o wn
t
IS
m o d e
t
PDEX
t
I S
N O P
Active
PDEX
E n t e r Ac ti v e
p o we r- d o wn
t
IS
N O P
m o d e
prior to Row active command. Refresh
Revision : 1.4
Publication Date : Sep. 2008
t
X S R ( m i n )
N O P
M53D128168A
Active
E n t e r A c t i v e
p o w e r -d o wn
t
IS
m o d e
N O P
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