as7c331mntf32a Alliance Memory, Inc, as7c331mntf32a Datasheet - Page 4

• Manufacturer Part Number: as7c331mntf32a
• Description: 3.3v 32/36 Flowthrough Sram With
• Manufacturer: Alliance Memory, Inc

Functional Description
The AS7C331MNTF32A/36A family is a high performance CMOS 32 Mbit synchronous Static Random Access Memory
(SRAM) organized as 1,048,576 words × 32 or 36 bits and incorporates a LATE Write.
This variation of the 32Mb+ synchronous SRAM uses the No Turnaround Delay (NTD
write operation that improves bandwidth over flowthrough burst devices. In a normal flowthrough burst device, the write data,
command, and address are all applied to the device on the same clock edge. If a read command follows this write command,
the system must wait for one dead cycle for valid data to become available. This dead cycle can significantly reduce overall
bandwidth for applications requiring random access or read-modify-write operations.
NTD
through read latency. Write data is applied one cycle after the write command and address, allowing the read pipeline to clear.
With NTD
Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 36
bit writes. Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied
to the device one clock cycle later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write
operations; it can be tied low for normal operations. Outputs go to a high impedance state when the device is de-selected by
any of the three chip enable inputs.
Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chip
select, R/W pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any
device operations, including burst, can be stalled using the CEN=1, the clock enable input.
The AS7C331MNTF32A/36A operates with a 3.3V ± 5% power supply for the device core (V
power supply (V
TQFP Capacitance
*Guranteed not tested
TQFP thermal resistance
1 This parameter is sampled
Input capacitance
I/O capacitance
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to top of case)
12/23/04, v 1.2
™
devices use the memory bus more efficiently by introducing a write latency which matches the one-cycle flow-
Parameter
Description
™
, write and read operations can be used in any order without producing dead bus cycles.
DDQ
1
) that operates across 3.3V or 2.5V ranges. These devices are available in a 100-pin TQFP package a.
1
Test conditions follow standard test methods and
procedures for measuring thermal impedance,
Symbol
C
C
I/O
IN
*
*
per EIA/JESD51
Conditions
Alliance Semiconductor
Test conditions
V
in
V
= V
in
= 0V
out
= 0V
®
1–layer
4–layer
™
Min
Symbol
) architecture, featuring an enhanced
-
-
θ
θ
θ
JA
JA
JC
AS7C331MNTF32A/36A
DD
). DQ circuits use a separate
Typical
Max
40
22
5
7
8
P. 4 of 18
°C/W
°C/W
°C/W
Units
Unit
pF
pF