as7c331mntf32a Alliance Memory, Inc, as7c331mntf32a Datasheet - Page 6

• Manufacturer Part Number: as7c331mntf32a
• Description: 3.3v 32/36 Flowthrough Sram With
• Manufacturer: Alliance Memory, Inc

Burst order
Synchronous truth table
Key: X = Don’t Care, H = HIGH, L = LOW. BWn = H means all byte write signals (BWa, BWb, BWc, and BWd) are HIGH. BWn = L means one or more
byte write signals are LOW.
Notes:
1 CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or WRITE) is chosen in the ini-
2 DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation. A WRITE ABORT means a
3 OE may be wired LOW to minimize the number of control signal to the SRAM. The device will automatically turn off the output drivers during a WRITE
4 If an INHIBIT CLOCK command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it occurs during a WRITE cycle, the bus will
5
6 All inputs except
7 Wait states are inserted by setting
8 This device contains circuitry that will ensure that the outputs will be in High-Z during power-up.
9 The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth BURST CYCLE.
10 The address counter is incremented for all CONTINUE BURST cycles.
11 ZZ pin is always Low.
CE0 CE1 CE2 ADV/LD R/W
WRITE command is given, but no operation is performed.
cycle. OE may be used when the bus turn-on and turn-off times do not meet an application’s requirements.
BW
tial BEGIN BURST cycle. A CONINUE DESELECT cycle can only be entered if a DESELECT CYCLE is executed first.
remain in High-Z. No WRITE operations will be performed during the INHIBIT CLOCK cycle.
enables WRITEs to byte “d” (DQd pins).
Second increment
H
X
X
X
X
X
X
X
X
L
L
L
L
12/23/04, v 1.2
Third increment
Starting address
First increment
a enables WRITEs to byte “a” (DQa pins);
X
X
L
X
H
X
H
X
H
X
H
X
X
Interleaved burst order LBO = 1
X
H
X
X
X
X
X
X
X
L
L
L
L
OE
and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
H
H
H
H
H
X
L
L
L
L
L
L
L
A1 A0
0 0
0 1
1 0
1 1
[5,6,7,8,9,11]
CEN
X
X
X
X
H
X
H
X
X
X
X
L
L
HIGH.
A1 A0
0 1
0 0
1 1
1 0
BWn
X
X
X
X
X
X
X
X
H
H
X
L
L
BW
A1 A0
b enables WRITEs to byte “b” (DQb pins);
1 0
1 1
0 0
0 1
OE CEN
X
X
X
X
H
H
X
X
X
X
X
L
L
Alliance Semiconductor
A1 A0
H
L
L
L
L
L
L
L
L
L
L
L
L
1 1
1 0
0 1
0 0
External L to H NOP/DUMMY READ (Begin Burst) High-Z
External L to H
External L to H
External L to H NOP/WRITE ABORT (Begin Burst) High-Z
Address
Current L to H
source
Next
Next
Next
Next
NA
NA
NA
NA
Second increment
Starting Address
Third increment
First increment
®
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
CLK
Linear burst order LBO = 0
DUMMY READ (Continue Burst)
WRITE CYCLE (Continue Burst)
WRITE ABORT (Continue Burst)
BW
CONTINUE DESELECT Cycle
READ Cycle (Continue Burst)
WRITE CYCLE (Begin Burst)
READ Cycle (Begin Burst)
c enables WRITEs to byte “c” (DQc pins);
A1 A0
DESELECT Cycle
DESELECT Cycle
DESELECT Cycle
INHIBIT CLOCK
0 0
0 1
1 0
1 1
Operation
AS7C331MNTF32A/36A
A1 A0
1 0
1 1
0 0
0 1
A1 A0
1 0
1 1
0 0
0 1
P. 6 of 18
A1 A0
High-Z
High-Z
High-Z
High-Z
High-Z 1,2,10
High-Z
1 1
0 0
0 1
1 0
DQ
BW
Q
Q
D
D
-
d
1,3,10
1,2,3,
Notes
1,10
2,3
10
2
4
1
3