as7c331mpfs32a Alliance Memory, Inc, as7c331mpfs32a Datasheet - Page 4

• Manufacturer Part Number: as7c331mpfs32a
• Description: 3.3v 32/36 Pipelined Burst Synchronous Sram
• Manufacturer: Alliance Memory, Inc

Functional description
The AS7C331MPFS32A/36A is a high-performance CMOS 32-Mbit Synchronous Static Random Access Memory (SRAM)
device organized as 1,048,576 words x 32/36. It incorporates a two-stage register-register pipeline for highest frequency on any
given technology.
Fast cycle times of 5/6/7.5 ns with clock access times (t
Three chip enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller
address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally
generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip
address register when ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In
a read operation, the data accessed by the current address registered in the address registers by the positive edge of CLK are
carried to the data-out registers and driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock
edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally for the next
access of the burst when ADV is sampled low and both address strobes are high. Burst mode is selectable with the
With
uses a linear count sequence.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable
GWE writes all 32/36 bits regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is high, one or more
bytes may be written by asserting BWE and the appropriate individual byte BWn signals.
BWn is ignored on the clock edge that samples ADSP low, but it is sampled on all subsequent clock edges. Output buffers are
disabled when BWn is sampled LOW regardless of OE. Data is clocked into the data input register when BWn is sampled low.
Address is incremented internally to the next burst address if BWn and ADV are sampled low. This device operates in single-
cycle deselect feature during read cycles.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC
and ADSP follow.
ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
WE signals are sampled on the clock edge that samples ADSC low (and ADSP high).
Master chip enable CE0 blocks ADSP, but not ADSC.
The AS7C331MPFS32A/36A family operates from a core 3.3V power supply. I/Os use a separate power supply that can
operate at 2.5V or 3.3V. These devices are available in a 100-pin TQFP package.
TQFP capacitance
* Guaranteed not tested
TQFP thermal resistance
1 This parameter is sampled
Input capacitance
I/O capacitance
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to top of case)
12/23/04,
LBO
Parameter
Description
unconnected or driven high, burst operations use an interleaved count sequence. With
v.2.9
1
1
Symbol
C
C
I/O
IN
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51
*
*
Test conditions
Alliance Semiconductor
V
V
OUT
Conditions
IN
= 0V
= 0V
CD
) of 3.1/3.5/3.8 ns enable 200,166and 133MHz bus frequencies.
®
Min
-
-
1–layer
4–layer
Max
5
7
Symbol
θ
θ
θ
Unit
JA
JA
JC
pF
pF
AS7C331MPFS32A
AS7C331MPFS36A
LBO
driven low, the device
Typical
40
22
8
4 of 19
LBO
Units
°C/W
°C/W
°C/W
input.