as7c331mpfs32a Alliance Memory, Inc, as7c331mpfs32a Datasheet - Page 6

• Manufacturer Part Number: as7c331mpfs32a
• Description: 3.3v 32/36 Pipelined Burst Synchronous Sram
• Manufacturer: Alliance Memory, Inc

Write enable truth table (per byte)
Key: X = don’t care, L = low, H = high, n = a, b, c, d;
Asynchronous Truth Table
Notes:
1. X means “Don’t Care”
2. ZZ pin is pulled down internally
3. For write cycles that follows read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur.
4. Snooze mode means power down state of which stand-by current does not depend on cycle times
5. Deselected means power down state of which stand-by current depends on cycle times
Burst sequence table
Write All Bytes
Write Byte a
Write Byte c and d
Read
Snooze mode
Read
Write
Deselected
Starting Address
First Increment
Second Increment
Third Increment
12/23/04,
Operation
Function
v.2.9
Interleaved burst address (LBO = 1)
A1 A0
ZZ
GWE
0 0
0 1
1 0
1 1
H
L
L
L
L
H
H
H
H
H
L
A1 A0
BWE
0 1
0 0
1 1
1 0
X
H
L
L
L
L
OE
X
H
X
X
L
BWE
BWa
Alliance Semiconductor
A1 A0
1 0
1 1
0 0
0 1
X
H
X
H
L
L
Din, High-Z
,
I/O Status
BWn
High-Z
High-Z
High-Z
Dout
BWb
= internal write signal.
A1 A0
X
H
H
X
H
L
1 1
1 0
0 1
0 0
BWc
X
H
X
H
L
L
Starting Address
First Increment
Second Increment
Third Increment
®
BWd
X
H
X
H
L
L
Linear burst address (LBO = 0)
A1 A0
0 0
0 1
1 0
1 1
AS7C331MPFS32A
AS7C331MPFS36A
A1 A0
0 1
1 0
1 1
1 0
A1 A0
1 0
1 1
0 0
0 1
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A1 A0
1 1
0 0
0 1
1 0