as7c331mpfs18a Alliance Memory, Inc, as7c331mpfs18a Datasheet - Page 16

• Manufacturer Part Number: as7c331mpfs18a
• Description: 3.3v Pipelined Burst Synchronous Sram
• Manufacturer: Alliance Memory, Inc

AC test conditions
Notes
1
2
3
4
5
6
8
7
12/23/04, v 2.6
• Output load: For t
• Input pulse level: GND to 3V. See Figure A.
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.5V.
+3.0V
For test conditions, see “AC Test Conditions”, Figures A, B, and C.
This parameter is measured with output load condition in Figure C.
This parameter is sampled but not 100% tested.
t
t
This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must
meet the setup and hold times for all rising edges of CLK when chip is enabled.
Write refers to GWE, BWE, and BW[a,b]
Chip select refers to CE0, CE1, and CE2.
GND
HZOE
CH
Figure A: Input waveform
10%
is measured as high above VIH, and t
is less than t
90%
LZOE
LZC
, and t
, t
90%
LZOE
10%
HZC
, t
is less than t
HZOE
D
OUT
CL
.
, t
is measured as low below VIL.
HZC
LZC
Figure B: Output load (A)
, see Figure C. For all others, see Figure B.
at any given temperature and voltage.
Alliance Semiconductor
Z
0
= 50Ω
50Ω
30 pF*
®
V
for 3.3V I/O;
V
for 2.5V I/O
L
L
= 1.5V
= V
DDQ
/2
353Ω/1538Ω
D
OUT
Figure C: Output load(B)
Thevenin equivalent:
AS7C331MPFS18A
319Ω/1667Ω
5 pF*
GND
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
*including scope
and jig capacitance
16 of 19