as7c331mpfs18a Alliance Memory, Inc, as7c331mpfs18a Datasheet - Page 6

• Manufacturer Part Number: as7c331mpfs18a
• Description: 3.3v Pipelined Burst Synchronous Sram
• Manufacturer: Alliance Memory, Inc

Write enable truth table (per byte)
Key: X = don’t care; L = low; H = high; B
Asynchronous Truth Table
Notes:
1. X means “Don’t Care”
2. ZZ pin is pulled down internally
3. For write cycles that follows read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur.
4. Snooze mode means power down state of which stand-by current does not depend on cycle times
5. Deselected means power down state of which stand-by current depends on cycle times
Burst sequence table
Snooze mode
Read
Write
Deselected
Starting Address
First Increment
Second Increment
Third Increment
12/23/04, v 2.6
Write all bytes (a, b)
Write byte b
Write byte a
Operation
Function
Read
Interleaved burst address (LBO = 1)
A1 A0
ZZ
0 0
0 1
1 0
1 1
H
L
L
L
L
GWE
H
H
H
L
H
H
WE, BWn
A1 A0
0 1
0 0
1 1
1 0
OE
X
H
X
L
X
= internal write signal
Alliance Semiconductor
A1 A0
1 1
0 0
1 0
0 1
Din, High-Z
I/O Status
BWE
High-Z
High-Z
High-Z
Dout
X
H
L
L
L
L
A1 A0
1 1
1 0
0 1
0 0
Starting Address
First Increment
Second Increment
Third Increment
®
BWa
X
H
X
H
L
L
Linear burst address (LBO = 0)
BWb
X
H
X
H
A1 A0
L
L
0 0
0 1
1 0
1 1
AS7C331MPFS18A
A1 A0
0 1
1 0
1 1
1 0
A1 A0
1 0
1 1
0 0
0 1
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A1 A0
1 1
0 0
0 1
1 0