as7c164 Alliance Memory, Inc, as7c164 Datasheet - Page 6

• Manufacturer Part Number: as7c164
• Description: Static Random Access Memory
• Manufacturer: Alliance Memory, Inc

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10 CE1 or WE must be High or CE2 Low during address transitions. Either CE or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 CE1 and CE2 have identical timing.
13 2V data retention applies to the commercial operating range only.
14 C = 30pF, except on High Z and Low Z parameters, where C = 5pF.
Parameter
V
Data retention current
Chip enable to data retention time
Operation recovery time
- Output load: see Figure B or Figure C.
- Input pulse level: GND to 3.0V. See Figure A.
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
CC
During V
This parameter is sampled, but not 100% tested.
For test conditions, see AC Test Conditions, Figures A, B, and C.
t
This parameter is guaranteed, but not 100% tested.
WE is High for read cycle.
CE1 and OE are Low and CE2 is High for read cycle.
Address valid prior to or coincident with CE1 transition Low and CE2 transition High.
All read cycle timings are referenced from the last valid address to the first transitioning address.
V
CE1
CLZ
CS2
for data retention
CC
+3.0V
GND
and t
CC
CHZ
power-up, a pull-up resistor to V
10%
are specified with CL = 5pF as in Figures B or C. Transition is measured 500mV from steady-state voltage.
Figure A: Input pulse
90%
2ns
90%
10%
V
V
V
CC
IH
IH
CC
$OOLDQFH 6HPLFRQGXFWRU
on CE1 is required to meet I
t
t
CDR
t
t
CDR
Symbol
V
I
CCDR
CDR
R
DR
Figure B: 5V Output lo
D
255
Data retention mode
V
DR
V
V
SB
CE1
DR
DR
specification.
2.0V
Test conditions

+5V
480
C
GND
Š
V
CE2 0.2V
(14)
CC
V
= 2.0V
CC
–0.2V or
D
Figure C: 3.3V Output load
D
Thevenin Equivalent:
Min
2.0
–
0
t
V
255
RC
V
V
CC
IH
IH
168
t
t
R
R
+1.728V (5V)
+5V
320
C
GND
Max
–
60
–
–
(14)
$6&
Unit
V
µA
ns
ns