as7c4096a Alliance Memory, Inc, as7c4096a Datasheet - Page 5

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as7c4096a

Manufacturer Part Number
as7c4096a
Description
5.0v 512k ? 8 Cmos Sram
Manufacturer
Alliance Memory, Inc
Datasheet

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Write cycle (over the operating range)
Write waveform 1 (WE controlled)
Write cycle time
Chip enable (CE) to write end
Address setup to write end
Address setup time
Write pulse width (OE = high)
Write pulse width (OE = low
Address hold from end of write
Write recovery time
Data valid to write end
Data hold time
Write enable to output in high Z
Output active from write end
2/21/06, v 1.2
Address
D
OUT
D
WE
IN
Parameter
t
AS
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
WP1
WP2
DW
OW
WC
CW
AW
WR
WZ
AH
DH
AS
9
t
Min
WZ
Alliance Semiconductor
10
10
7
7
0
7
0
0
5
0
2
3
9
–10
t
AW
Max
t
WC
5
t
WP
Min
12
12
8
8
0
8
0
0
6
0
2
3
t
DW
Data valid
–12
®
Max
6
Min
15
10
10
10
15
t
0
0
0
7
0
2
3
OW
–15
t
t
t
WR
AH
DH
Max
7
Min
20
12
12
12
20
0
0
0
9
0
2
3
–20
Max
9
AS7C4096A
Unit Notes
P. 5 of 10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3,4
3,4
3,4

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