as6c2016 Alliance Memory, Inc, as6c2016 Datasheet - Page 8

• Manufacturer Part Number: as6c2016
• Description: Static Random Access Memory
• Manufacturer: Alliance Memory, Inc

WRITE CYCLE 3
Notes :
1.WE#,CE#, LB#, UB# must be high during all address transitions.
2.A write occurs during the overlap of a low CE#, low WE#, LB# or UB# = low.
3.During a WE# controlled write cycle with OE# low, t
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the CE#, LB#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance
6.t
LB#,UB#
Address
placed on the bus.
state.
OW
WE#
Dout
CE#
Din
FEBRUARY/2008, V 1.c
January 2007
FEBRUARY 2008
and t
WHZ
are specified with C
(LB#
,UB#
t
AS
Controlled)
L
= 5pF. Transition is measured ±500mV from steady state.
(4)
128K X 16 BIT LOW POWER CMOS SRAM
t
WHZ
(1,2,5,6)
Alliance Memory Inc.
WP
t
AW
must be greater than t
t
t
CW
WP
t
WC
t
BW
512K X 8 BIT LOW POWER CMOS SRAM
t
DW
High-Z
WHZ
Data Valid
+ t
DW
to allow the drivers to turn off and data to be
t
WR
t
DH
Page 8 of 13
AS6C2016