bs62uv256 Brillance Semiconductor, bs62uv256 Datasheet - Page 7

• Manufacturer Part Number: bs62uv256
• Description: Ultra Low Power Cmos Sram 32k X 8 Bit
• Manufacturer: Brillance Semiconductor

R0201-BS62UV256
WRITE CYCLE 2
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals
3. t
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
6. OE is continuously low (OE = V
7. D
8. D
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of
10. Transition is measured ± 500mV from steady state with C
11. t
must be active to initiate a write and any one signal can terminate a write by going inactive. The
data input setup and hold timing should be referenced to the second transition edge of the
signal that terminates the write.
the outputs must not be applied.
transition, output remain in a high impedance state.
opposite phase to the outputs must not be applied to them.
The parameter is guaranteed but not 100% tested.
ADDRESS
CE
WE
D
D
WR
CW
OUT
OUT
OUT
IN
is measured from the earlier of CE or WE going high at the end of write cycle.
is measured from the later of CE going low to the end of write.
is the same phase of write data of this write cycle.
is the read data of next address.
(1,6)
IL
).
t
AS
(5)
t
WHZ
L
= 5pF.
(4,10)
t
AW
7
t
t
CW
WP
t
WC
(11)
(2)
t
DW
t
t
OW
DH
(8,9)
(7)
BS62UV256
Revision
Sep.
(8)
2006
2.6