cp3cn17 National Semiconductor Corporation, cp3cn17 Datasheet - Page 141
![no-image](/images/no-image-200.jpg)
cp3cn17
Manufacturer Part Number
cp3cn17
Description
Reprogrammable Connectivity Processor With Can Interface
Manufacturer
National Semiconductor Corporation
Datasheet
1.CP3CN17.pdf
(220 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
cp3cn17K38
Manufacturer:
Texas Instruments
Quantity:
10 000
Company:
Part Number:
cp3cn17K38/NOPB
Manufacturer:
Texas Instruments
Quantity:
10 000
- Current page: 141 of 220
- Download datasheet (4Mb)
Acknowledge Cycle
The Acknowledge Cycle consists of two signals: the ac-
knowledge clock pulse the master sends with each byte
transferred, and the acknowledge signal sent by the receiv-
ing device (Figure 71).
The master generates the acknowledge clock pulse on the
ninth clock pulse of the byte transfer. The transmitter releas-
es the SDA line (permits it to go high) to allow the receiver
to send the acknowledge signal. The receiver must pull
down the SDA line during the acknowledge clock pulse,
which signals the correct reception of the last data byte, and
its readiness to receive the next byte. Figure 72 illustrates
the acknowledge cycle.
The master generates an acknowledge clock pulse after
each byte transfer. The receiver sends an acknowledge sig-
nal after every byte received. There are two exceptions to
the “acknowledge after every byte” rule.
SDA
SCL
by Transmitter
Data Output
Data Output
by Receiver
When the master is the receiver, it must indicate to the
transmitter an end-of-data condition by not-acknowledg-
ing (“negative acknowledge”) the last byte clocked out of
the slave. This “negative acknowledge” still includes the
acknowledge clock pulse (generated by the master), but
the SDA line is not pulled down.
When the receiver is full, otherwise occupied, or a prob-
lem has occurred, it sends a negative acknowledge to in-
dicate that it cannot accept additional data bytes.
Figure 72. ACCESS.bus Acknowledge Cycle
Start
Condition
S
Figure 71. ACCESS.bus Data Transaction
SCL
MSB
1
Start
Condition
S
2
3 - 6
Interrupt Within
Byte Complete
1
7
Receiver
2
8
3 - 6
ACK
9
Acknowledgment
Signal from Receiver
7
1
8
Clock Line Held
Low by Receiver
While Interrupt
is Serviced
2
9
Transmitter Stays Off
the Bus During the
Acknowledgment Clock
Acknowledgment
Signal from Receiver
3-8
ACK
9
Condition
DS078
DS077
Stop
P
141
Addressing Transfer Formats
Each device on the bus has a unique address. Before any
data is transmitted, the master transmits the address of the
slave being addressed. The slave device should send an
acknowledge signal on the SDA signal, once it recognizes
its address.
The address is the first seven bits after a Start Condition.
The direction of the data transfer (R/W) depends on the bit
sent after the address (the eighth bit). A low-to-high transi-
tion during a SCL high period indicates the Stop Condition,
and ends the transaction (Figure 73).
Figure 73. A Complete ACCESS.bus Data Transaction
When the address is sent, each device in the system com-
pares this address with its own. If there is a match, the de-
vice considers itself addressed and sends an acknowledge
signal. Depending upon the state of the R/W bit (1 = read,
0 = write), the device acts as a transmitter or a receiver.
The ACCESS.bus protocol allows sending a general call ad-
dress to all slaves connected to the bus. The first byte sent
specifies the general call address (00h) and the second byte
specifies the meaning of the general call (for example,
“Write slave address by software only”). Those slaves that
require the data acknowledge the call and become slave re-
ceivers; the other slaves ignore the call.
Arbitration on the Bus
Arbitration is required when multiple master devices attempt
to gain control of the bus simultaneously. Control of the bus
is initially determined according to address bits and clock
cycle. If the masters are trying to address the same bus de-
vice, data comparisons determine the outcome of this arbi-
tration. In master mode, the device immediately aborts a
transaction if the value sampled on the SDA lines differs
from the value driven by the device. (Exceptions to this rule
are SDA while receiving data; in these cases the lines may
be driven low by the slave without causing an abort.)
The SCL signal is monitored for clock synchronization and
allows the slave to stall the bus. The actual clock period will
be the one set by the master with the longest clock period
or by the slave stall period. The clock high period is deter-
mined by the master with the shortest clock high period.
When an abort occurs during the address transmission, the
master that identifies the conflict should give up the bus,
switch to slave mode, and continue to sample SDA to see if
it is being addressed by the winning master on the AC-
CESS.bus.
SDA
SCL
Start
Condition
S
Address
1 - 7
R/W
8
ACK
9
1 - 7
Data
8
ACK
9
1 - 7
Data
www.national.com
8
ACK
9
Condition
DS079
Stop
P
Related parts for cp3cn17
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![mma1270keg](/images/no-image3.png)
Part Number:
Description:
Freescale Semiconductor Technical Data
Manufacturer:
National Semiconductor Corporation
Datasheet:
![ADC12034](/images/no-image3.png)
Part Number:
Description:
Self-calibrating 12-bit Plus Sign Serial I/o A/d Converters With Mux And Sample/hold
Manufacturer:
National Semiconductor Corporation
Datasheet:
![LMX2350](/images/no-image3.png)
Part Number:
Description:
Pllatinum Tm Fractional N Rf / Integer N If Dual Low Power Frequency Synthesizer
Manufacturer:
National Semiconductor Corporation
Datasheet:
![LMX2324](/images/no-image3.png)
Part Number:
Description:
Pllatinum? 2.0 Ghz Frequency Synthesizer For Rf Personal Communications
Manufacturer:
National Semiconductor Corporation
Datasheet:
![LMX2301](/images/no-image3.png)
Part Number:
Description:
Pllatinumtm 160 Mhz Frequency Synthesizer For Rf Personal Communications
Manufacturer:
National Semiconductor Corporation
Datasheet:
![NDS8963](/images/no-image3.png)
Part Number:
Description:
Dual N-channel Enhancement Mode Field Effect Transistor
Manufacturer:
National Semiconductor Corporation
Datasheet:
![LM1201](/images/no-image3.png)
Part Number:
Description:
Video Amplifier System (obsolete)
Manufacturer:
National Semiconductor Corporation
Datasheet:
![LM3501TL-16](/images/no-image3.png)
Part Number:
Description:
Synchronous Step-up DC/DC Converter For White Led Applications
Manufacturer:
National Semiconductor Corporation
Datasheet:
![AD9621](/images/no-image3.png)
Part Number:
Description:
CLC420 - High Speed, Voltage Feedback op Amp, Package: Lcc, Pin Nb=20
Manufacturer:
National Semiconductor Corporation
Datasheet:
![LM2403](/images/no-image3.png)
Part Number:
Description:
Monolithic Triple 4.5 CRT Driver
Manufacturer:
National Semiconductor Corporation
Datasheet:
![LM592M](/images/no-image3.png)
Part Number:
Description:
Differential Video Amplifier
Manufacturer:
National Semiconductor Corporation
Datasheet:
![ADC10061](/images/no-image3.png)
Part Number:
Description:
ADC10061 - 10-Bit 600 NS A/D Converter With Input Multiplexer And Sample/Hold, Package: Soic Wide, Pin Nb=20
Manufacturer:
National Semiconductor Corporation
Datasheet:
![DS36277TMX](/images/no-image3.png)
Part Number:
Description:
DS36277 - Dominant Mode Multipoint Transceiver, Package: Soic Narrow, Pin Nb=8
Manufacturer:
National Semiconductor Corporation
Datasheet:
![DS3654](/images/no-image3.png)
Part Number:
Description:
Printer Solenoid Driver
Manufacturer:
National Semiconductor Corporation
Datasheet:
![DS3662](/images/no-image3.png)
Part Number:
Description:
Quad High Speed Trapezoidal Bus Transceiver
Manufacturer:
National Semiconductor Corporation
Datasheet: