cp3cn17 National Semiconductor Corporation, cp3cn17 Datasheet - Page 166

• Manufacturer Part Number: cp3cn17
• Description: Reprogrammable Connectivity Processor With Can Interface
• Manufacturer: National Semiconductor Corporation

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Figure 86 illustrates the configuration of a timer subsystem
while operating in capture mode. The numbering in
Figure 86 refers to timer subsystem 1 but equally applies to
the other three timer subsystems.
23.1.4
In case a timer subsystem is not used, software can place it
in a low-power mode. All clocks to a timer subsystem are
stopped and the counter and prescaler contents are frozen
once low-power mode is entered. Software may continue to
write to the MODE, INTCTL, IOxCTL, and CLKxPS regis-
ters. Write operations to the INTPND register are allowed;
but if a timer subsystem is in low-power mode, its associat-
ed interrupt pending bits cannot be cleared. Software can-
not write to the COUNTx, PERCAPx, and DTYCAPx
registers of a timer subsystem while it is in low-power mode.
All registers can be read at any time.
23.1.6
The VTU supports breakpoint operation of the In-System-
Emulator (ISE). If FREEZE is asserted, all timer counter
clocks will be inhibited and the current value of the timer reg-
IxAPD
IxBPD
IxCPD
IxDPD
Pending Flag
Figure 86. VTU Dual 16-bit Capture Mode
Low Power Mode
ISE Mode operation
cap
rst
15
2
C1EDG
Restart
0
Low Byte Duty Cycle match
Low Byte Period match
High Byte Duty Cycle match
High Byte Period match
TIO1
Dual 8-bit PWM Mode
PERCAP1[15:0]
DTYCAP1[15:0]
7
Count1[15:0]
T1RUN
Compare
Compare
Prescaler
C1PRSC
Counter
= =
Table 66 VTU Interrupt Sources
cap
0
rst
2
C2EDG
TMOD1=11
0
DS092
TIO2
0
15:0
166
23.1.5
The VTU has a total of 16 interrupt sources, four for each of
the four timer subsystems. All interrupt sources have a
pending bit and an enable bit associated with them. All in-
terrupt pending bits are denoted IxAPD through IxDPD
where “x” relates to the specific timer subsystem. There is
one system level interrupt request for each of the four timer
subsystems.
Figure 87 illustrates the interrupt structure of the versatile
timer module.
Each of the timer pending bits - IxAPD through IxDPD - is
set by a specific hardware event depending on the mode of
operation, i.e., PWM or Capture mode. Table 66 outlines the
specific hardware events relative to the operation mode
which cause an interrupt pending bit to be set.
isters will be frozen; in capture mode, all further capture
events are disabled. Once FREEZE becomes inactive,
counting will resume from the previous value and the cap-
ture input events are re-enabled.
Period match
N/A
N/A
Duty Cycle match
I1AEN
I1BEN
I1CEN
I1DEN
I1APD
I1BPD
I1CPD
I1DPD
I4AEN
I4BEN
I4CEN
I4DEN
I4APD
I4BPD
I4CPD
I4DPD
16-bit PWM Mode
Figure 87. VTU Interrupt Request Structure
Interrupts
Counter Overflow
Capture to PERCAPx
Capture to DTYCAPx
N/A
Capture Mode
System
Interrupt
Request 1
System
Interrupt
Request 4
DS093