cx50331 Chip Express Corporation, cx50331 Datasheet

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cx50331

Manufacturer Part Number
cx50331
Description
0.18-?m Structured Asic
Manufacturer
Chip Express Corporation
Datasheet
1.CX50331.pdf (6 pages)
Product Description
The 0.18- m CX5000 is an ASIC that uses the combination of an
advanced metal programmable gate array and optimized EDA system to
implement high performance ASIC designs, while reducing application
tooling costs and design turnaround time. ASIC designers using the
CX5000 are able to meet or exceed their design schedules and budgets
without compromising technical objectives.
The CX5000 comprises a family of pre-configured platform product that
contain varying amounts of general-purpose logic, fast memory, advanced
I/Os, clock synthesis and phase management macrocells. When combined with a mix of popular
third-party tools and custom-designed point EDA solutions, the CX5000 provides not just gate
array hardware, but also a complete ASIC platform from which to develop today’s advanced SoC
ASICs.
Manufactured in UMC’s 0.18- m, 6-layer metal CMOS process, the CX5000 combines the
reliability and quality of an industry-leading silicon foundry, with the high performance, low power
consumption and fast design turnaround time of ChipX Structured ASIC technology. The CX5000
family is very applicable to cost reduction projects, replacing expensive FPGA devices with
low-cost metal programmable technology. The CX5000 is the first viable “standard cell
alternative” ASIC technology, developed in response to the growing need for cost-effective ASIC
implementation capability.
The CX5000 Structured ASIC technology uses just two of the six available metal layers to
program the logic, memory, I/O, and clocking of an ASIC design, thus eliminating the large costs
of the remaining “fixed” masks. Wafers are manufactured up to Metal 4, where they are held
pending completion of the customer application. Completed chips can be delivered to the
customer less than three weeks after sign-off of the finished design.
ChipX Structured ASIC technology is very similar in concept to FPGA, which makes it easy to
use and familiar to most ASIC and system designers. Using metal interconnect segments rather
than SRAM cells to program the ASIC, CX5000 technology reduces the area of the chip by
between 5x and 10x over the equivalent FPGA and brings performance up to 90% of standard
cell design speeds.
Key Features and Benefits








January 16, 2007
Structured ASIC architecture
Low NRE and start-up costs
Fast time to production
90K to 578K usable ASIC gates
Up to 1.2M bits of fast block memory
2 ns access time single-port SRAM, dual-port SRAM and ROM
Low power consumption (0.06 W/MHz/gate)
200 MHz general core logic operation, 650 MHz in constrained clock domains
CX5000
0.18- m Structured ASIC
0247-5k-080-C
Data Sheet
1 of 6

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cx50331 Summary of contents

Page 1

CX5000 0.18- m Structured ASIC Product Description The 0.18- m CX5000 is an ASIC that uses the combination of an advanced metal programmable gate array and optimized EDA system to implement high performance ASIC designs, while reducing application tooling costs ...

Page 2

... Max Usable ASIC Base Array Gates (K) CX50101 90–101 CX50211 131–144 CX50331 207–228 CX50561 336–369 CX50841 526–578 There are a fixed number of block memories on each product for speed, and for logic and memory efficiency. Each product has a total available memory count, which can be split into either 18K, 16K blocks in a variety of widths and depths, or double-pumped to create smaller memories ...

Page 3

CX5000 0.18- m Structured ASIC The CX5000 family has a flexible I/O structure. Each metal-programmable I/O driver cell supports one or two pads, depending on the I/O configuration chosen. The CX5000 product line can be packaged in conventional IC packaging, ...

Page 4

CX5000 0.18- m Structured ASIC Figure 1 CX5000 CX-Memory Configurations ƒÃU‚à SX Q‚…‡Ã6 #ÃU‚Ã%# #ÃU‚Ã%# SX Q‚…‡Ã7 ƒÃU‚à Corner Figure 2 illustrates the CX5000 die corner that contains a number of important analog components. Each corner contains an accurate bandgap ...

Page 5

CX5000 0.18- m Structured ASIC Figure 2 Analog PL I/O Ring As shown in Figure 3, the CX5000 I/O ring is comprised of blocks of 8 metal programmable I/O drivers, 16 pads and ESD structures. Each I/O structure may be ...

Page 6

CX5000 0.18- m Structured ASIC Table 3 CX5000 Supported I/O I/O Standard Vdd LVTTL25/33 2.5 V/3.3 V LVCMOS25/33 2.5 V/3.3 V PCI 3.3 V PCI-X 3.3 V USB 3.3 V LVDS 3.3 V LVPECL 3.3 V SSTL2/3 2.5 V/3.3 V ...

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