cx50331 Chip Express Corporation, cx50331 Datasheet - Page 2

• Manufacturer Part Number: cx50331
• Description: 0.18-?m Structured Asic
• Manufacturer: Chip Express Corporation

The CX5000 Structured ASIC Product
The CX5000 product line is designed to incorporate a mix of gates and memory optimized for a
wide range of today’s advanced SoCs. With a ratio of approximately 160% memory to gates,
each product contains enough memory to support CPU cache, network rate-matching FIFOs,
multiple video line buffers and various other single- or dual-port applications.
The CX5000 product array shown in Table 1 has a variety of gate and memory counts. The
maximum usable gates in each array is design-dependent, and refers to the actual size of a
customer design prior to test insertion or timing closure.
Table 1
There are a fixed number of block memories on each product for speed, and for logic and
memory efficiency. Each product has a total available memory count, which can be split into
either 18K, 16K, or 8K blocks in a variety of widths and depths, or double-pumped to create
smaller memories. The memory can be configured as single- or dual-port RAM/ROM, as
required.
ChipX uses the latest clock synthesis techniques during layout of the Structured ASIC. We
provide the user with four complete analog PLL units for clock phase alignment (when needed),
frequency synthesis, or stabilization. These PLL macros have excellent jitter performance and
incorporate all of the analog components needed for supply and loop filtering on board the
product. A DLL macro generator is available for clock-edge alignment in timing-critical
applications.
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CX5000
0.18- m Structured ASIC
PCI, PCI-X, SSTL, HSTL, USB1.1, RSDS, LVPECL and LVDS up to 622 Mbps
1.5 V or 1.8 V or mixed supply voltage operation
Up to 1100 total pads
Low-jitter analog PLL macros with internal loop filter
Delay Lock Loop (DLL) macros for clock de-skewing
Wide range of synthesizable IP cores such as CPUs and interface controllers
Vast packaging library
Standard ASIC tool flow
Available front-end and FPGA conversion design services
BIST and Scan synthesis test options
Seamless migration to Standard Cell in high volume
Excellent for SoC designs, new ASICs, and FPGA conversion
Base Array
CX50101
CX50211
CX50331
CX50561
CX50841
CX5000 Product Array
Max Usable ASIC
Gates (K)
131–144
207–228
336–369
526–578
90–101
Fast Block SRAM (K) Low Jitter APLL/DLL
0247-5k-080-C
1264
880
160
364
518
4/12
4/12
4/8
4/8
4/8
ChipX Data Sheet
January 16, 2007
Bond Pads
256
384
448
640
768