cx50331 Chip Express Corporation, cx50331 Datasheet - Page 4
![no-image](/images/no-image-200.jpg)
cx50331
Manufacturer Part Number
cx50331
Description
0.18-?m Structured Asic
Manufacturer
Chip Express Corporation
Datasheet
1.CX50331.pdf
(6 pages)
Figure 1 CX5000 CX-Memory Configurations
Corner
Figure 2 illustrates the CX5000 die corner that contains a number of important analog
components. Each corner contains an accurate bandgap device, which is then used to provide
reference and bias voltages to other components in the pad ring. Also contained in each corner is
a complete, programmable analog PLL.
The PLL may be configured to operate at frequencies between 7.5 MHz and 500 MHz, given
certain input clock criteria and loop filter choices. ChipX provides an automatic response server
that will reply with simulation and synthesis macros for a specific frequency PLL based on the
input frequency, desired output frequency, and phase relationship. The PLL models may be
easily disabled and bypassed to reduce simulation time.
ChipX CX5000 logic is fast when compared to standard FPGA logic, so it is possible to create all
of the counters, dividers, and clock phase taps from synthesized logic rather than relying on
custom macros. The corner also contains an ESD structure that is used in concert with the ESD
structures adjacent to the pads to provide 2.5 KV of ESD protection to the devices.
4 of 6
CX5000
0.18- m Structured ASIC
Q
Ã6
Q
Ã7
SX
SX
ÃUÃ
ÃUÃ
#ÃUÃ%#
#ÃUÃ%#
HrhyÃQ
t
hhiyr
HrhyÃQ
t
hhiyr
6qq
rÃ9rpqr
Ã6
6qq
rÃ9rpqr
Ã7
#%#
#%#
"!
"!
0247-5k-080-C
!$%Ã6qq
rrÃÃ%#Ã7v
!$%
!$%
HrhyÃ
t
hhiyr
Ã
Ã!ÃHr
ÃDhpr
S6HÃ8ryyÃ6
h
Dr
prp
!ÃTvtyrÃQ
ÃS6HSPH
Ã9hyÃQ
ÃTS6H
ChipX Data Sheet
January 16, 2007