ak4644 AKM Semiconductor, Inc., ak4644 Datasheet - Page 70

• Manufacturer Part Number: ak4644
• Description: Stereo Codec With Mic/hp/rcv-amp
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
MS0477-E-01
Addr
Addr
03H
04H
Addr
05H
MINL: Switch Control from MIN pin to Stereo Line Output or Receiver Output
MGAIN1: MIC-Amp Gain Control (See Table 23)
LOPS: Stereo Line Output Power-Save Mode
LOVL: Stereo Line Output / Receiver Output Gain Select (See Table 48, Table 49)
DIF1-0: Audio Interface Format (See Table 17)
BCKO: BICK Output Frequency Select at Master Mode (See Table 11)
PLL3-0: PLL Reference Clock Select (See Table 5)
FS3-0: Sampling Frequency Select (See Table 6 and Table 7) and MCKI Frequency Select (See Table 12.)
BCKP: BICK Polarity at DSP Mode (See Table 18)
MSBS: LRCK Polarity at DSP Mode (See Table 18)
PS1-0: MCKO Output Frequency Select (See Table 10)
0: OFF (Default)
1: ON
0: Normal Operation (Default)
1: Power-Save Mode
0: 0dB/+6dB (Default)
1: +2dB/+8dB
Default: “10” (Left jutified)
Default: “0000”(LRCK pin)
“0”: SDTO is output by the rising edge (“↑”) of BICK and SDTI is latched by the falling edge (“↓”). (Default)
“1”: SDTO is output by the falling edge (“↓”) of BICK and SDTI is latched by the rising edge (“↑”).
“0”: The rising edge (“↑”) of LRCK is half clock of BICK before the channel change. (Default)
“1”: The rising edge (“↑”) of LRCK is one clock of BICK before the channel change.
Default: “00”(256fs)
Register Name
Signal Select 2
Register Name
Mode Control 1
Register Name
Mode Control 2
When PMLO bit is “1”, MINL bit is enabled. When PMLO bit is “0”, the LOUT/ROUT pins go to AVSS.
FS3-0 bits select sampling frequency at PLL mode and MCKI frequency at EXT mode.
Default
Default
Default
LOVL
PLL3
PS1
D7
D7
D7
0
0
0
LOPS
PLL2
D6
PS0
D6
0
D6
0
0
- 70 -
MGAIN1
PLL1
D5
FS3
0
D5
D5
0
0
MSBS
PLL0
D4
0
0
D4
D4
0
0
BCKO
BCKP
D3
0
0
D3
D3
0
0
MINL
D2
FS2
D2
0
D2
0
0
0
DIF1
FS1
D1
D1
D1
0
0
0
1
[AK4644]
2006/10
DIF0
FS0
D0
D0
D0
0
0
0
0