ak4644 AKM Semiconductor, Inc., ak4644 Datasheet - Page 91

• Manufacturer Part Number: ak4644
• Description: Stereo Codec With Mic/hp/rcv-amp
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
MS0477-E-01
Receiver-amp Output
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). When the AK4644 is PLL mode, DAC and Receiver-Amp should be
(2) Set up the path of “DAC
(3) Set up the input digital volume (Addr: 09H and 0CH)
(4) Set up the output digital volume (Addr: 0AH and 0DH).
(5) Power Up of DAC, MIN-Amp and Receiver-Amp: PMDAC = PMMIN = PMLO bits = “0” → “1”
(6) Exit the power-save-mode of Receiver-Amp: LOPS bit = “1” → “0”
(7) Enter the power-save-mode of Receiver-Amp: LOPS bit = “0” → “1”
(8) Disable the path of “DAC
(9) Power Down DAC, MIN-Amp and Receiver-Amp: PMDAC = PMMIN = PMLO bits = “1” → “0”
When PMADL = PMADR bits = “0”, IVL7-0 and IVR7-0 bits should be set to “91H”(0dB).
When DVOLC bit is “1” (default), DVL7-0 bits set the volume of both channels. After DAC is powered-up, the
digital volume changes from default value (0dB) to the register setting value by the soft transition.
The DAC enters an initialization cycle that starts when the PMDAC bit is changed from “0” to “1” at PMADL
and PMADR bits are “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization
cycle, the DAC input digital data of both channels are internally forced to a 2’s compliment, “0”. The DAC
output reflects the digital input data after the initialization cycle (1059/fs=24ms@fs=44.1kHz) is complete.
When PMADL or PMADR bit is “1”, the DAC does not require an initialization cycle.
powered-up in consideration of PLL lock time after a sampling frequency is changed.
(Addr:05H, D5&D2-0)
(Addr:09H&0CH, D7-0)
(Addr:0AH&0DH, D7-0)
(Addr:02H, D4)
(Addr:21H, D0)
(Addr:00H, D2)
(Addr:00H, D5)
(Addr:00H, D3)
(Addr:03H, D6)
PMDAC bit
DVL/R7-0 bits
PMMIN bit
IVL/R7-0 bits
DACL bit
PMLO bit
LOPS bit
FS3-0 bits
RCP pin
RCN pin
RCV bit
0,000
Hi-Z
E1H
18H
(2)
(4)
(3)
Hi-Z
(1)
(5)
Figure 82. Receiver-Amp Output Sequence
RCV-Amp and Power-save mode”: DACL=LOPS bit = “0”
(6)
RCV-Amp”: DACL bit = “1”
(7)
VCOM
(8)
Normal Output
Normal Output
91H
1,111
28H
- 91 -
(9)
VCOM
(10)
Hi-Z
(11)
Hi-Z
“0”
Example:
PLL Master Mode
Audio I/F Format: MSB justified (ADC & DAC)
Sampling Frequency: 44.1kHz
Digital Volume: −8dB
LOVL = MINL bits = “0”
(1) Addr:05H, Data:27H
(2) Addr:21H, Data:01H
(3) Addr:02H, Data:10H
(4) Addr:03H, Data:40H
(5) Addr:09H & 0CH, Data:91H
(6) Addr:0AH & 0DH, Data:28H
(10) Addr:02H, Data:00H
(11) Addr:00H, Data:40H
(7) Addr:00H, Data:6CH
(9) Addr:03H, Data:40H
(8) Addr:03H, Data:00H
Playback
“1”
[AK4644]
2006/10