ak4644 AKM Semiconductor, Inc., ak4644 Datasheet - Page 88

• Manufacturer Part Number: ak4644
• Description: Stereo Codec With Mic/hp/rcv-amp
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
MS0477-E-01
(Addr:05H, D5&D2-0)
(Addr:00H&10H, D0)
ALC Control 1
ALC Control 2
ALC Control 3
ALC Control 4
(Addr:02H, D2-0)
ADC Internal
MIC Input Recording (Stereo)
MIC Control
PMADL/R bit
<Example>
ALC State
FS3-0 bits
(Addr:0BH)
(Addr:07H)
(Addr:06H)
(Addr:08H)
This sequence is an example of ALC setting at fs=44.1kHz. If the parameter of the ALC is changed, please refer to
“Figure 36. Registers set-up sequence at ALC operation”
State
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bit). When the AK4644 is PLL mode, MIC and ADC should be powered-up
(2) Set up MIC input (Addr: 02H)
(3) Set up Timer Select for ALC (Addr: 06H)
(4) Set up REF value for ALC (Addr: 08H)
(5) Set up LMTH1 and RGAIN1 bits (Addr: 0BH)
(6) Set up LMTH0, RGAIN0, LMAT1-0 and ALC bits (Addr: 07H)
(7) Power Up MIC and ADC: PMADL = PMADR bits = “0” → “1”
(8) Power Down MIC and ADC: PMADL = PMADR bits = “1” → “0”
(9) ALC Disable: ALC bit = “1” → “0”
When the registers for the ALC operation are not changed, ALC bit may be keeping “1”. The ALC operation is
disabled because the MIC&ADC block is powered-down. If the registers for the ALC operation are also changed
when the sampling frequency is changed, it should be done after the AK4644 goes to the manual mode (ALC bit
= “0”) or MIC&ADC block is powered-down (PMADL=PMADR bits = “0”). IVOL gain is not reset when
PMADL=PMADR bits = “0”, and then IVOL operation starts from the setting value when PMADL or PMADR
bit is changed to “1”.
in consideration of PLL lock time after a sampling frequency is changed.
The initialization cycle time of ADC is 1059/fs=24ms@fs=44.1kHz.
After the ALC bit is set to “1” and MIC&ADC block is powered-up, the ALC operation starts from IVOL
default value (+30dB).
The time of offset voltage going to “0” after the ADC initialization cycle depends on both the time of analog
input pin going to the common voltage and the time constant of the offset cancel digital HPF. This time can be
shorter by using the following sequence:
At first, PMVCM and PMMP bits should set to “1”. Then, the ADC should be powered-up. The wait time to
power-up the ADC should be longer than 4 times of the time constant that is determined by the AC coupling
capacitor at analog input pin and the internal input resistance 60k(typ).
0,000
E1H
07H
00H
00H
001
(1)
ALC Disable
Power Down
(2)
(3)
(4)
(5)
(6)
Figure 79. MIC Input Recording Sequence
(7)
Initialize Normal State Power Down
1059 / fs
1,111
ALC Enable
3CH
E1H
00H
101
21H
- 88 -
(8)
ALC Disable
(9)
01H
Example:
Audio I/F Format:MSB justified (ADC & DAC)
Pre MIC AMP:+20dB
MIC Power On
PLL Master Mode
Sampling Frequency:44.1kHz
ALC setting:Refer to Table 35
ALC bit=“1”
(1) Addr:05H, Data:27H
(3) Addr:06H, Data:3CH
(4) Addr:08H, Data:E1H
(2) Addr:02H, Data:05H
(5) Addr:0BH, Data:00H
(6) Addr:07H, Data:21H
(7) Addr:00H, Data:41H
(8) Addr:00H, Data:40H
(9) Addr:07H, Data:01H
Addr:10H, Data:01H
Addr:10H, Data:00H
Recording
[AK4644]
2006/10