ak4620b AKM Semiconductor, Inc., ak4620b Datasheet - Page 31

• Manufacturer Part Number: ak4620b
• Description: 24-bit 192khz Audio Codec With Ipga
• Manufacturer: AKM Semiconductor, Inc.

Addr
ASAHI KASEI
01H
MS0401-E-00
Addr
02H
RSTDA: DAC reset
RSTAD: ADC reset
AML, AMR: default “0” (see
DCKB: Polarity of DCLK (DSD Only)
DCKS: Master Clock Frequency Select at DSD mode (DSD only)
D/P: DSD/PCM Mode Select
DFS1-0: Sampling Speed Control (see Table 2)
CMODE, CKS1-0: Master Clock Frequency Select (see Table 3)
DIF2-0: Audio data interface modes (see Table 9)
Register Name
Reset Control
Register Name
Clock and Format Control
0: Reset (Default)
1: Normal Operation
0: Reset (Default)
1: Normal Operation
0: DSD data is available upon DCLK falling edge. (Default)
1: DSD data is available upon DCLK rising edge.
0: 512fs (Default)
1: 768fs
0: PCM mode (Default)
1: DSD mode
000: Mode 0
001: Mode 1
010: Mode 2 (Default)
011: Mode 3
100: Mode 4
“0” resets the internal timing and the AOUTs go to VCOM voltage immediately. The contents of all registers
are not initialized and enabled to write to the registers. After exiting the power down mode, the OATTs fade in
the setting values of the control register (06H & 07H). The analog outputs should be muted externally since
pop noise may occur when entering to and exiting from this mode.
“0” resets the internal timing and then SDTO goes to “L” immediately. The IPGAs also go “00H”, but the
contents of all registers are not initialized and enabled to write to the register. After exiting the power down
mode, the IPGAs fade in the setting value of the control register (04H & 05H). At that time, the ADCs output
“0” during first 516 LRCK cycles.
DEFAULT
DEFAULT
Default: Normal speed
Default: 256fs
Default: 24bit MSB justified for both ADC and DAC
Table 16
DIF2
D/P
D7
D7
0
0
)
DCKS
DIF1
D6
D6
0
1
- 31 -
DCKB
DIF0
D5
D5
0
0
CMODE
D4
D4
0
0
0
CKS1
AML
D3
D3
0
0
CKS0
AMR
D2
D2
0
0
RSTAD
DFS1
D1
D1
0
0
[AK4620B]
2005/07
RSTDA
DFS0
D0
D0
0
0