ml7033 Oki Semiconductor, ml7033 Datasheet - Page 23

• Manufacturer Part Number: ml7033
• Description: Dual-channel Line Card Codec
• Manufacturer: Oki Semiconductor

The event detected by the SLIC is determined by the F2_n, F1_n, and F0_n register bits (CR6-B7 to B5/CR13-
B7 to B5), and the E0_n register bits (CR6-B2 /CR13-B2). To avoid the unintended detection of these conditions
due to glitches on the DETn signal of the SLIC, the ML7033 is equipped with a debounce timer to hold the DET
register bit (CR6-B1/CR13-B1) and the output of the INT pin for a set period, even when an input to the DETn
pin changes from a logic “1” to a logic “0”. For more information on the debounce timer, refer to the
DETnTIM3 through DETnTIM0 register bit descriptions (CR4-B7 to B0).
This pin remains functional in power-down mode (PDN pin low). However, while in the power-down state, the
debounce timer is disabled.
When this pin is not used, it should be tied to V
ALM1, ALM2
The ALMn pins are the thermal shut down alarm signals. These pins are used when the SLIC connected to the
corresponding channel is an Intersil RSLIC
corresponding ALM register bit (CR6-B0/CR13-B0). A logic “1” on this pin sets the bit.
The Intersil RSLIC
mode and toggle its ALMn pin from a logic “1” to a logic “0” state when the SLIC die temperature exceeds a
safe operating temperature. Hence, by connecting the corresponding pin of the SLIC device to the ALM1 and
ALM2 pins and reading the ALM register bit (CR6-B0/CR13-B0), it is possible to know whether the concerned
SLIC device is operating normally, or is in a thermal shutdown state.
This pin remains functional in power-down mode. However, while in the power-down state, the debounce timer
is disabled.
When this pin is not used, it should be tied to V
INT
The ML7033 asserts the INT interrupt pin when either the DETn pin or the ALMn pin are asserted by the SLIC
device when the device is an Intersil RSLIC
equipped with detector and thermal shut down alarm functions to notify a change of SLIC state by driving a
logic 0 onto the output pins connected to DETn and ALMn. Refer to the DETn and ALMn pin descriptions
above. By monitoring the state of the INT pin and reading the DETn (CR6-B0/CR13-B0) and ALMn (CR6-
B0/CR13-B0) register bits, it is possible to know that a change of a state occurred within the SLIC device.
The INT pin transitions from a logic “1” to a logic “0” in the following cases;
(1) (PDN pin = logic “0”) Any of the ALMn or DETn pins in the logic “1” state transition to the logic “0”
(2) (PDN pin = logic “1”) Any of the ALMn or DETn pins transition from the logic “1” state to the logic “0”
Note that the debounce timer with the DETn pin is not valid while in power-down mode (PDN pin = logic “0”).
1 Semiconductor
state.
state when all the four pins (ALM1, ALM2, DET1, and DET2) have been in the logic “1” state.
TM
series device is equipped with a function that allows it to automatically enter power-down
TM
DDD
DDD
TM
series device. A logic “0” on the ALMn input pin clears the
.
.
series SLIC device. The Intersil RSLIC
TM
series device is
FEDL7033-02
ML7033
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