ml7033 Oki Semiconductor, ml7033 Datasheet - Page 30

• Manufacturer Part Number: ml7033
• Description: Dual-channel Line Card Codec
• Manufacturer: Oki Semiconductor

CR4 (Debounced timer setting)
B7 to B4
B3 to B0
1 Semiconductor
default
CR4
To avoid the unintended detection of glitches on the DETn signal, the ML7033 is equipped with
a debounce timer to hold the DETn (CR6-B1/CR13-B1) bit and the INT output state for a set
period, even when the state of the DETn pin changes from logic “1” to logic “0”. Bits B7 to B4
determine the debounce timer setting for CH2. Bits B3 to B0 determine the debounce timer
setting CH1.
The debounce timer is operational only in the power-on state when the PDN pin = logic “1”,
and remains operational in the power-saving mode with the MODEn (CR0-B1, B0) bits = “0” as
long as the device is in the power-on state.
The debounce timer holding time ranges from 0 ms to 225 ms at 15 ms intervals for each
individual channel. The values written into B7 to B4 (channel 2) or B3 to B0 (channel 1)
determine the holding time for each channel.
The timer value is calculated by the equation of [Decimal(B7,B6,B5,B4) * 15] or
[Decimal(B3,B2,B1,B0) * 15]. Refer to Table 8.
DET2
TIM3
… Debounce timer setting for CH2
… Debounce timer setting for CH1
B7
0
B7/B3
0
0
0
0
0
0
1
1
1
:
:
DET2
TIM2
B6
0
Table 8 Debounce Timer Setting
B6/B2
0
0
0
0
1
1
0
0
1
:
:
DET2
TIM1
B5
0
B5/B1
0
0
1
1
0
1
0
0
1
:
:
DET2
TIM0
B4
0
B4/B0
0
1
0
1
0
1
0
1
1
:
:
DET1
TIM3
B3
0
Timer (ms)
105
120
135
225
DET1
15
30
45
60
TIM2
0
:
:
B2
0
DET1
TIM1
B1
0
FEDL7033-02
ML7033
DET1
TIM0
B0
0
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