ml7033 Oki Semiconductor, ml7033 Datasheet - Page 32

• Manufacturer Part Number: ml7033
• Description: Dual-channel Line Card Codec
• Manufacturer: Oki Semiconductor

CR6 (SLIC 1 control)
*
*
B7 to B5
B4
B3
B2
1 Semiconductor
CR6-B1 and B0 are read-only bits. Though either of “0” or “1” will do for these registers when a byte-wide write action is
made, the written values are ignored.
The INT pin which stays at logic “0” will be released to logic “1” when both of this control register (CR6) and SLIC 2
control register (CR13) are read.
default
CR6
F2_1
… Operation mode setting for SLIC1
… Uncommitted switch control for SLIC1
… Battery mode select for SLIC1
… Detector mode selection for SLIC1
B7
0
The F2_1 to F0_1 bits determine the output level for the Fn_1 pins. For more details, refer
to Table 6. When each bit is cleared (“0”), the corresponding Fn_1 pin outputs a logic “0”.
When each bit is set (“1”), the corresponding Fn_1 pin outputs a logic “1”.
This bit determines the output level for the SWC1 pin. When this bit is cleared, the SWC1
pin outputs a logic “0”. When this bit is set, the pin outputs a logic “1”.
When the SLIC connected to CH1 is the Intersil RSLIC
uncommitted switch, located between the SW+ pin and the SW- pin, can be controlled by
inputting the output from the SWC1 pin directly into the corresponding input pin of the
SLIC device.
This bit determines the output level for the BSEL1 pin. When this bit is cleared, the BSEL1
pin outputs a logic “0”. When this bit is set, the pin outputs a logic “1”.
When the SLIC connected to CH1 is from the Intersil RSLIC
mode selection is possible by inputting the output from the BSEL1 pin directly into the
corresponding input pin of the SLIC device.
This bit determines the output level for the E0_1 pin. When this bit is cleared, the E0_1 pin
outputs a logic “0”. When this bit is set, the pin outputs a logic “1”.
When a SLIC connected to CH1 is Intersil RSLIC
selection is possible by connecting the E0_1 pin directly to the corresponding input pin of
the SLIC device. The event detected by the SLIC is determined by the combination of the
F2_1, the F1_1, the F0_1 and the E0_1 pins as shown in Table 6.
The output level of the E0_1 pin changes 20 s later (hold timer) in the power-on mode with
the PDN pin = logic “1”, and 200ns later in the power-down mode with the PDN pin =
logic “0” than a change of this bit value. Refer to Figure 6.
F1_1
B6
0
F0_1
B5
0
SWC1
B4
0
0 : low battery mode
BSEL1
B3
0
0 : switch on
TM
series, the SLIC’s detector mode
E0_1
B2
0
TM
TM
series, the SLIC’s internal
1 : high battery mode
series, the SLIC’s battery
1 : switch off
DET1
B1
—
FEDL7033-02
ML7033
ALM1
B0
—
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