mt8926ap Mitel, mt8926ap Datasheet - Page 8

• Manufacturer Part Number: mt8926ap
• Description: Iso-cmos T1 Performance Monitoring Adjunct Circuit Pmac
• Manufacturer: Mitel

MT8926
MT8926 FDL message transfer. This 16 bit pattern
must be detected in seven out of 10 codewords in
order for the RAI bit of Master Status Word 1 (CSTo
channel 15 bit 4) to go high (see Table 3). If more
than three out of 10 codewords are in error, then RAI
will remain low.
A low to high transition of the RAI bit will initiate a
group one (G1) interrupt. See the section on
interrupts for the control of the RAI interrupt.
Loss of Signal Indication (LOS)
The LOS bit of Master Status Word 1, Table 3, will be
high if the MT8926 receives 128 or more consecutive
zeros from the T1 interface. LOS will return low when
a ones density of 12.5% has been achieved
4-10
7-5
Bit
4
3
2
1
0
BOMV
Name
LLDD
FECV
LLED
TMR
---
Table 5. PMAC Miscellaneous Status Word (CSTo Channel 7)
Not Used.
Line Loopback Disable Detect. This bit is set when a repeating 001 pattern (either
framed or unframed) is detected in the received T1 signal for at least five frames.
In order to comply with T1.403, the user's operating system will ensure that this
code is present for at least five seconds before deactivating the SF line loopback
(MT8976/77 Remote Loopback).
The MT8926 will detect this repeating bit pattern even in the presence of a BER of
3 errors in 1000 bits.
Line Loopback Enable Detect. This bit is set when a repeating 00001 pattern
(either framed or unframed) is detected in the received T1 signal for at least five
frames. In order to comply with T1.403, the user's operating system will ensure
that this code is present for at least five seconds before activating the SF line
loopback (MT8976/77 Remote Loopback).
The MT8926 will detect this repeating bit pattern even in the presence of a BER of
3 errors in 1000 bits.
Framing Error Count Validation. This bit is set when the MT8926 has synchronized
to a framed T1 signal. The framing error count is frozen if this bit is not set.
Synchronization (FECV=1) is reported when the MT8926 detects two consecutive
superframes with correct framing bits, and bit 0 in CSTi0 channel 15 (SYN) is zero.
When receiving an SF signal, both F
the PMAC Control word is set. In this case the sixth F
checking for framing bits. If bit FSel is reset, then only F
Loss of synchronization (FECV=0) is reported when either two out of four errors
have been detected in the received framing bit position (SF F
bits) or if bit 0 in CSTi0 channel 15 (SYN) is set indicating the MT8976/77 has lost
synchronization.
Two Second Timer. This bit changes state once per second.
Bit-Oriented Message Validation. This bit will be set when a valid bit-oriented
message is present in the receive BOM register (Table 12, CSTo, channel 27). It is
reset when a valid message is not being received. A valid bit-oriented message
has the form 111111110XXXXXX0, where XXXXXX contains the message
information.
(approximately 48 ones is received in two or less
frames).
Payload Loopback
The payload of a T1 signal consists of the 192 data
bits of each frame and excludes the framing bit (the
first bit of 193). Therefore, a T1.403 or T1.408 ESF
payload loopback extracts the payload of a receive
T1 signal and transmits it back to the originator with
new framing bits. This allows the transport of
maintenance and performance data over the facility
data link while the payload loopback is activated.
The CRC-6 multiframe alignment remainder will not
be looped around, but will function normally (i.e.,
calculated for each direction of transmission).
Description
S
and F
T
bits are examined if bit 3 (FSel) in
S
bit is not examined when
T
bits are examined.
T
bits or ESF FPS
)