mt90520 Zarlink Semiconductor, mt90520 Datasheet
mt90520
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mt90520 Summary of contents
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... Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2002-2006, Zarlink Semiconductor Inc. All Rights Reserved. Circuit Emulation AAL1 SAR Ordering Information MT90520AG MT90520AG2 456 Pin PBGA** Trays, Bake & **Pb Free Tin/Silver/Copper Residual Time Stamp (SRTS) via 8 independent PLLs • ...
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... Mbps. The configurable TDM ports interface directly with DS1 or E1 framers for Nx64 Structured operation, or with DS1 or E1 LIUs in Unstructured mode. On the ATM interface side, the MT90520 device meets the ATM Forum standard for UTOPIA Bus Level 2. The MT90520 is capable of operating as a UTOPIA “master” (ATM-end), “slave” (PHY-end), or “multi-PHY slave” (PHY- end) ...
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... MT90520 UTOPIA 8-Port CES SAR Port UTOPIA ATM or PHY Device Optional AAL5 SAR in PHY mode Figure 2 - MT90520 Device Application Block Diagram MT90520 * NOTE: Structured CES applications require a framer CPU and LIU (or integrated framer-LIU); Unstructured CES applications require only an LIU Port 0 Framer ...
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... Global Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.1.2 CPU Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.2 External Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.3 TDM Interface Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.3.1.1 Segmentation Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.3.1.2 Reassembly Direction 4.3.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.3.2.1 Segmentation Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.3.2.2 Reassembly Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.3.2.3 TDM Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.4 UTOPIA Interface Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.4.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.4.1.1 Segmentation Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.4.1.2 Reassembly Direction 4.5 TX_SAR Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 MT90520 Table of Contents 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Test Access Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 4.8.2 JTAG 107 4.8.3 Boundary Scan Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 4.8.4 BSDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.0 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 5.1 Internal Memory Map 108 5.2 External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.0 Registers 112 6.1 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 6.2 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 6.2.1 Microprocessor Interface Module 118 6.2.2 TX_SAR Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 MT90520 Table of Contents 5 Zarlink Semiconductor Inc. Data Sheet ...
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... Power-Up and Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 8.1.2 External Memory Interface Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 8.1.3 UTOPIA Interface Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 8.2 Segmentation and Reassembly Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 9.0 Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 9.1 Normative Standards 175 9.2 Informative Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 10.0 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 10.1 Glossary References 178 MT90520 Table of Contents 6 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 1 - MT90520 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - MT90520 Device Application Block Diagram Figure 3 - MT90520 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 4 - PCB Pad Diagram for PBGA (JEDEC MO-151 Figure 5 - Aerial View of Package Specifications Figure 6 - Side View of Package Specification Figure 7 - Sample Interrupt Generation (for Data RX_SAR Module Figure 8 - Memory Read Pipeline Length ...
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... Figure 66 - UTOPIA Level 2 Interface Timing - PHY Mode - Outgoing Data (UTOPIA RX Bus 167 Figure 67 - External Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Figure 68 - ATM Mode: External UTOPIA Pin Connections 170 Figure 69 - PHY Mode: External UTOPIA Pin Connections 171 MT90520 List of Figures 8 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 29 - High Address Indirection Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 30 - Indirection Data Register 119 Table 31 - Main Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Table 32 - MT90520 Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Table 33 - TX_SAR Pointer Table Base Register (one per port 120 Table 36 - Data TX_SAR Read Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 34 - Data TX_SAR Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 35 - Data TX_SAR Write Pointer Register ...
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... Table 92 - External Memory Interface Timing - Read Cycle Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Table 93 - External Memory Interface Timing - Write Cycle Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Table 94 - TDM Bus Input Clock Parameters 158 Table 95 - TDM Bus Input Data Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Table 96 - TDM Bus Output Clock Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 MT90520 List of Tables 10 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 102 - UTOPIA Level 2 Interface Timing - PHY mode - Incoming Data (UTOPIA TX Bus 165 Table 103 - UTOPIA Level 2 Interface Timing - PHY mode - Outgoing Data (UTOPIA RX Bus 166 Table 104 - MT90520 UTOPIA Signal Directions 169 Table 105 - Segmentation Latency 172 Table 106 - Reassembly Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Table 107 - End-to-End Latency ...
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... MT90520 can be connected directly to a wide variety of industry-standard framers and LIUs (line interface units 2.048 Mbps ST-BUS TDM backplane. At its interface to the ATM network, the MT90520 supports a wide selection of UTOPIA-compliant Physical layer devices, and customer-specific ASICs which meet the UTOPIA (Level 1 or Level 2) specification ...
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... RX SARs (UDT, SDT, Data) Local PLL Memory Rx/Reassembly (X 8) Registers Boundary- Microprocessor Scan Logic Interface Logic 16-bit Microprocessor Interface JTAG Interface Figure 3 - MT90520 Block Diagram 13 Zarlink Semiconductor Inc. Data Sheet External Synchronous ZBT SRAM CSTi/LOSi TDM DSTi INPUT STiCLK BLOCK STiMF ...
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... UTOPIA Level 2 compliant 16-bit or 8-bit bus, capable of running MHz • Accepts data rate 622 Mbps • Supports both “master” (ATM-end) and “slave” (PHY-end) operation • Supports multi-PHY (MPHY) mode when operating as a PHY device MT90520 14 Zarlink Semiconductor Inc. Data Sheet ...
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... Support for optional external PLL such as MT9042 or MT9044: primary & secondary network references and primary & secondary LOS references output to external PLL; TDM_CLOCK input from external PLL • Bus clock I/O for operation in backplane mode: C4M/C2M and F0. MT90520 15 Zarlink Semiconductor Inc. Data Sheet ...
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... Interrupts • Wide variety of interrupt source bits, allowing for easy monitoring of MT90520 operation • Associated enable bits which enable or disable assertion of the service request and, ultimately, the IRQ interrupt pin 2.10.1 Module Level Service Requests 2 ...
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... Per-port Cut VC Alarm • Per-port Late Cell Arrival Alarm 2.11 Statistics The MT90520 provides a number of statistics to allow monitoring of the MT90520. These statistics generally parallel the operation of some of the service request source bits. 2.11.1 TDM Module • Per-port Simple Underrun Channel Indicator - status field indicates which channel of the TDM port last experienced a simple underrun (SDT mode only) • ...
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... Per-VC Lost Cell Counter • Per-VC Misinserted Cell Counter • Per-VC Pointer Reframe Counter • Per-VC Pointer Parity Error Counter • Per-VC Write Underrun Counter • Per-VC Write Overrun Counter • Overall SDT Cell Counter MT90520 18 Zarlink Semiconductor Inc. Data Sheet ...
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... D10, C9, B9, A9, 0] D11, E11, C10, B10, A10, C11, B11, D12 C12 RDY/DTACK A11 IRQ Table 1 - Microprocessor Interface Pins MT90520 I/O Type I 3.3 V This input selects the microprocessor interface mode as Intel (pulled HIGH) or Motorola (pulled LOW). This pin CMOS PD must be configured before power-up ...
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... Active LOW memory chip select signal for bank 2. This signal is used to enable memory bank 2 when 2 or more banks of external RAM are connected to the MT90520. 3 Active LOW memory chip select signal for bank 3. This signal is used to enable memory bank 3 when 4 banks of external RAM are connected to the MT90520 ...
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... W1,U3, R2, N3, L3 AE1,AB3, AA2, SToCLK[7:0] W3, T4, T1, M5, L1 AF2, AD1, SToMF[7:0] AB1, Y2, T5, T3, P4, M1 MT90520 I/O Type I 3.3 V PCM Input Clocks. These inputs are used to sample the incoming PCM CMOS PD data/CAS from the E1 or DS1 lines. In Structured CES mode, ST-BUS format STiCLK is 4.096 MHz; Generic format STiCLK is 1.544 MHz or 2.048 MHz for DS1 ...
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... Pin Name AE2, AB4, Y4, DSTo[7:0] V4, V1, T2, P1, M3 AF1, AC2, CSTo/ AA3, Y1, V2, LOSo[7:0] P5, P2, M2 MT90520 I/O Type O 3.3 V, Serial PCM Data Outputs. In Unstructured CES mode, each pin carries 1.544 Mbps or 2.048 Mbps serial stream. In Structured CES mode, each pin carries a 1.544 Mbps or 2.048 Mbps serial stream which contains a 24-channel data stream in DS1 operation or a 32-channel data stream in E1 operation ...
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... PHY mode.) I 3.3 V CMOS Multi-PHY address signals. These address inputs are used to poll the MT90520 and to select the next MPHY device to PD receive data on UTO_IN_DATA. These signals are driven from the ATM-end to the PHY-end, and only used when the MT90520 is in PHY mode. (Inactive when the MT90520 is in ATM mode ...
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... Handshake output for UTO_OUT_DATA. When the MT90520 is in ATM mode, this output is TxEnb*, indicating that the data on UTO_OUT_DATA is valid. When the MT90520 is in PHY mode, this output is RxClav, indicating that the MT90520 has a complete cell ready to output on UTO_OUT_DATA. Table 4 - UTOPIA Bus Pins 24 Zarlink Semiconductor Inc ...
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... PRI_REF O A14 PRI_LOS O B13 SEC_REF O A13 SEC_LOS O MT90520 Type 3.3 V Clock input from external PLL, operating at DS1/E1/ST-BUS line rate. CMOS PD 3.3 V PRS-traceable clock input (8 kHz reference clock or 19.44 MHz clock from PHY network layer). CMOS PD 3 Backplane clock to be used when all 8 TDM ports are to have the same input and output clock ...
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... Note that internal reset activity is Schmitt synchronous to MCLK; this signal is latched PU internally and held, and MCLK must be applied to bring the MT90520 out of reset. The TRST pin (JTAG reset) should also be asserted LOW during chip reset. Also see RESET bit in Chip Wide Reset Register at address 0000h. ...
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... AA24, W25, U23, AD19, AE21, AD22, AC6, R22, P26, L26, L23, AA22, AA25, W23, V26, AE19, AF21, AF23, AD24, AB16, AD16, AD14, AF12, AF10, AD9, AE7, AF4 Table 6 - Master Clock, Test and Power Pins MT90520 Pin Name I/O Type VDD_2.5 V PWR Power for core logic. ...
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... TDM Interface 32 UTOPIA 30 Clock Management 2 Miscellaneous 32 Power & Ground - Total 121 3.2 Physical Pin Description 3.2.1 Pin Description by Ball Pin Number The following table lists each ball of the PBGA package and the corresponding functional pin name. MT90520 Output I/O Power ...
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... UTO_OUT_DATA[14] B4 UTO_OUT_DATA[10] B5 UTO_OUT_DATA[5] B6 UTO_OUT_DATA[1] B7 AEM B8 CPU_DATA[13] B9 CPU_DATA[9] B10 CPU_DATA[4] B11 CPU_DATA[1] B12 VSS Table 8 - Pinout by Ball Pin Number MT90520 Ball Pin # Pin Name B13 SEC_REF B14 PRI_REF B15 PHY_CLK B16 CPU_ADD[16] B17 CPU_ADD[13] B18 CPU_ADD[9] B19 CPU_ADD[5] B20 TCK B21 MEM_ADD[19] ...
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... G24 MEM_DATA[2] G25 MEM_DATA[0] G26 MEM_WR H1 UTO_IN_ENBATM_ CLAVPHY H2 UTO_IN_CLK H3 UTO_IN_DATA[15] H4 UTO_IN_DATA[11] H5 UTO_IN_DATA[7] H22 VDD_2.5V H23 MEM_DATA[1] Table 8 - Pinout by Ball Pin Number MT90520 Ball Pin # Pin Name H24 MEM_CS_3 H25 MEM_CS_2 H26 MEM_CS_1 J1 UTO_IN_ADD[3] J2 UTO_IN_ADD[2] J3 UTO_IN_ADD[1] J4 UTO_IN_DATA[14] J5 VDD_3.3V J22 MEM_DATA[7] J23 MEM_CS_4 ...
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... SToMF[3] T11 VSS T12 VSS T13 VSS T14 VSS T15 VSS T16 VSS T22 VDD_2.5V T23 NC T24 NC T25 NC T26 NC Table 8 - Pinout by Ball Pin Number MT90520 Ball Pin # Pin Name U1 STiCLK[3] U2 DSTi[3] U3 CSTi/LOSi[3] U4 DSTi[4] U5 VDD_3.3V U22 NC U23 NC U24 NC U25 NC U26 NC V1 DSTo[3] ...
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... AD8 TEST_IN AD9 NC AD10 NC AD11 NC AD12 NC AD13 TEST_IN AD14 NC AD15 TEST_IN AD16 NC AD17 TEST_IN AD18 TEST_OUT Table 8 - Pinout by Ball Pin Number MT90520 Ball Pin # Pin Name AD19 NC AD20 NC AD21 NC AD22 NC AD23 NC AD24 NC AD25 TEST_IN AD26 TEST_IN AE1 SToCLK[7] AE2 DSTo[7] AE3 ...
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... corner is identified by metallized markings. 1 Figure 4 - PCB Pad Diagram for PBGA (JEDEC MO-151) MT90520 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 5 - Aerial View of Package Specifications MT90520 ý01.00 (3X) REF 4.00*45×××× ...
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... Typ. Figure 6 - Side View of Package Specification DIM 34.80 D 2.20 E 0.50 F 0.60 Notes: 1) Dimensions are given in millimeters. 2) 456-pin BGA package complies to JEDEC Standard MO-151. MT90520 MIN MAX 1.27 (REF) 31.75 (REF) 35.20 2.46 0.70 0.90 Table 9 - Package Dimensions 35 Zarlink Semiconductor Inc. Data Sheet D E NOTES solder ball grid pitch ...
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... Chip Wide Reset Register (CWRR) at 0000h is set high, “latching” the reset state. No registers other than the CWRR can be accessed until the RESET bit is cleared. The steps to reset and restart the MT90520 are therefore: 1. Assert hardware reset by driving the RESET pin low, or initiate a software reset by writing 0001h to the CWRR at byte address 0000h ...
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... CPU Interrupts The CPU interrupt mechanism works in a common way for all modules. Each module of the MT90520 has a status register and a service request enable register. One or more additional status-related registers may also be located within a module’s address space. ...
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... Data RX_SAR Sta- tus Bits (2022h, bits<4:1>) AND AND OR AND AND Data RX_SAR Service Enable Bits (2020h, bits<4:1>) Figure 7 - Sample Interrupt Generation (for Data RX_SAR Module) MT90520 Main Status Register (0002h, bit<6>) AND 1 AND AND AND 1 AND AND AND Interrupt Enable Register (000Ah, bit< ...
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... External Memory Interface The external memory interface module of the MT90520 provides access to external memory devices by various MT90520 modules (i.e., TDM, TX_SAR, UTOPIA, SDT RX_SAR, Data RX_SAR) and by the CPU. The MT90520 can interface with both the pipelined and flow-through types of synchronous zero bus turnaround (ZBT) RAM ...
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... CPU interrupt to be generated due to the occurrence of a parity error on reads of external memory data. The external memory interface of the MT90520 supports Mword of external memory. The configuration is programmable via the Memory Arbiter Configuration Register at byte address 7000h, and some of the possible ...
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... TDM Interface Module The TDM Interface module of the MT90520 device is designed to interface to a time division multiplexed backplane bus, to external framers, and to external line interface units (LIUs). Thus, the TDM module can interface with buses which carry Nx64 kbps data or bit stream data. The TDM module is responsible for performing Structured Data Transfer with and without CAS, and Unstructured Data Transfer, as required to meet the CES specification, af-vtoa- 0078 ...
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... If no Loss of Signal is detected, the sampled data is written to the TDM Input Buffer, where it is read by the TX_SAR. On the other hand, upon detecting a Loss of Signal, the TDM module ignores the data input on DSTi and writes all ones data to the TDM Input Buffer, for transfer to the TX_SAR. MT90520 42 Zarlink Semiconductor Inc. ...
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... Figure 11. There is one circular buffer for each TDM channel and each buffer is 64 entries long. Port p - Channel 0 64 words Port p - Channel 31 64 words Figure 11 - Per-Port SDT Segmentation Circular Buffers MT90520 CAS Res TDM Byte Word Address of Start of Buffer = TDM_SEGMEN_BASE_ADD * 2048d ...
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... CAS - If CAS data is being processed, this field contains the nibble of data which was last received by this channel (i.e., in the previous multiframe). CAS data is repeated for an entire multiframe (i.e., 24 consecutive entries in DS1 case, 16 consecutive entries in E1 case). MT90520 44 Zarlink Semiconductor Inc. Data Sheet ...
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... SDT Reassembly Circular Buffers in external memory). These addresses in external memory are formed using the TDM_REASS_BASE_ADD field (located in TDM Control Register 3) and the addresses programmed in the TDM SDT Reassembly Control Structure. Refer to Table 11 for more information on how the addresses are formed. MT90520 CAS TDM Byte ...
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... Reassembly Circ. Buffer Add. and Size<9:4>, 9’b0} 1024 entries {TDM_REASS_BASE_ADD, Reassembly Circ. Buffer Add. and Size<9:5>, 10’b0} Table 11 - Formation of the Reassembly Circular Buffer Base Address MT90520 Word V (Valid): If this bit is set, the channel’s output on DSTo and CSTo is valid. If this 0 Add bit is ‘ ...
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... Internal to the MT90520 the underrun detection mechanism is dependent on the active channel order of the output TDM bus DSTo. Underrun is mis-reported on any channel (x) for which an upper channel (x+4) is not active on the same TDM port ...
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... V - The valid bits should be set for those channels which should be output on DSTo/CSTo. If the valid bit for a channel is not set, the output channel is tristated. • SU, I, and PU bits - These bits should be cleared. • Reassembly Circular Buffer Address bits - • bits<9:6> - These bits should be cleared as they are not used in loopback mode. MT90520 48 Zarlink Semiconductor Inc. Data Sheet ...
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... MT90520 interface is capable of operating MHz. The user can choose to have the UTOPIA interface emulate a PHY device or an ATM device. When the MT90520 is operating in PHY mode capable of being polled; this allows the ATM device accessing the MT90520 to operate in multi-PHY mode. ...
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... Segmentation Direction TX UTOPIA Interface The TX UTOPIA Interface’s primary function is to transmit ATM cells to devices outside the MT90520 chip, according to the ATM Forum’s Level 2 UTOPIA specification. The port can operate in either ATM or PHY mode. When the port is operating in ATM mode, it complies with the transmit portion of the ATM Forum specification; when operating in PHY mode, it complies with the receive portion of the specification ...
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... The role of the OAM & VPI/VCI filter sub-module is to limit unnecessary VPI/VCI comparison and look-up table accesses. The filter allows only certain cells to be written into the Receive UTOPIA FIFO of the MT90520 and discards unwanted cells. Unwanted cells fall into three categories: • ...
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... VPI and VCI fields are examined. If all the bits of the VPI field and all the bits of the VCI field are equal to zero, the cell is a filler cell (i.e., a null cell), and it is discarded. Otherwise, the processing of the cell continues in the Match and Match Enable filter. MT90520 External PHY or ATM Device ...
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... The Match and Match Enable filter can reduce the number of unnecessary look-up table accesses (and therefore unnecessary memory-access bandwidth) by eliminating cells with VPI/VCI combinations known not to be destined for the MT90520 device. The user is advised to set the VPI/VCI Match and Match Enable filter as narrowly as practical for the application. ...
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... If the cell is not carrying OAM data, the UTOPIA module sends the cell to the UDT RX_SAR for processing. If external memory is present in the system configuration containing the MT90520, any received cells whose headers do not match those in the UDT search registers are passed to the look-up table sub-module and are processed as detailed in the SDT Operation section that follows ...
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... The RX Parity sub-module’s role is to calculate the odd parity bit over UTO_IN_DATA[15:0] (over UTO_IN_DATA[7:0] when operating in 8-bit mode). The module then compares the internally calculated value with the one supplied by the external system on UTO_IN_PAR. If the parity bits do not match, a counter is incremented in the UTOPIA Parity Mismatches Register (400Eh). MT90520 55 Zarlink Semiconductor Inc. Data Sheet ...
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... VPI/VCI Concatenation Look-up Table Search “00” (unknown) “01” (CBR) NO YES UKSEL=1? Cell discarded Figure 18 - Overview of the UDT VCI/VPI Comparison and Look-up Table Filtering Process MT90520 FIFO 8 (search all ports) YES OAM UDT Match cell? on Port p? YES ...
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... TX_SAR Module The TX_SAR modules of the MT90520 device (consisting of the CBR-handling TX_SAR and the non-CBR Data TX_SAR) are primarily responsible for organizing TDM data into ATM cells. Since the cells contain constant-bit-rate traffic, they must be assembled at a rate which is synchronized to the 8 plesiochronous TDM ports. ...
Page 58
... PHY devices are usually responsible for the generation of header error checking values. The value contained in the UDF2 field is only transmitted in outgoing cells if the MT90520 is using a 16-bit UTOPIA interface. If the VC is going to be carrying RTS nibbles, the SE bit must be set, as detailed in the figure above ...
Page 59
... There must be one control structure for each SDT VC that the TX_SAR is to transmit. The format for the SDT Segmentation Control Structures is shown in Figure 22. SDT control structures may be located at any address within the internal memory space (starting at byte address 80000h) which is reserved for Segmentation Control Structures. MT90520 TX TX_SAR UTOPIA ...
Page 60
... Note 1: Fields which appear in dark grey are reserved fields which must be cleared by software upon initialization. Note 2: Fields which appear in light grey are those which are updated by hardware. Figure 22 - Segmentation Control Structure - SDT Format MT90520 Number of TDM Octets: Indicates the number of TDM octets required to fill the next Word 1 0 cell of the corresponding VC ...
Page 61
... When the read pointer is used to scatter the cell generation, the F (First) bit of the Segmentation Control Structure should be set to ‘0’. For example, when N=1 VCs are used possible for the MT90520 to handle up to 256 VCs simultaneously. In this case, each VC only needs to be serviced once every 47 frames (once enough data from the TDM channel has been received to complete an ATM cell) ...
Page 62
... VC. Figure 24 shows the complete segmentation data path in SDT mode, from the incoming TDM data bus to the outgoing UTOPIA data bus. MT90520 0 TXPTB_Pp Register<13:0> L (Last Valid Pointer): When set, indicates that the current pointer is the last valid pointer in the table ...
Page 63
... The Data TX_SAR can operate simultaneously with the generation of AAL1 CBR cells by the TX_SAR. 4.5.4.1 Mode of Operation The Data TX_SAR within the MT90520 must be enabled, by setting the Data TX_SAR Enable bit in the Data TX_SAR Control Register at address 103Eh. The user writes the cells to a buffer located in external memory. The address and size of this buffer are programmed in the DTCON register, located at address 1038h ...
Page 64
... Data TX_SAR’s read pointer is equal to the write pointer controlled by the CPU). The Transmit Cell Buffer Empty bit in the Data TX_SAR Status Register at 1042h can be enabled to cause an interrupt to be generated on IRQ. MT90520 64 Zarlink Semiconductor Inc. Data Sheet ...
Page 65
... RX_SAR Modules The RX_SAR modules of the MT90520 device (consisting of the UDT RX_SAR, the SDT RX_SAR, and the Data RX_SAR) are primarily responsible for the reassembly of TDM data extracted from CBR ATM cells. In addition, in certain modes of operation, the SDT RX_SAR extracts CAS data from received cells and sends that information, as well as multiframe indication signals, to the TDM module ...
Page 66
... At a high level of abstraction, Figure 26 shows the functionality implemented within the UDT RX_SAR and SDT RX_SAR reassembly paths of the MT90520. Within the “ATM Cell Processing” path there are a number of different steps which must be taken, depending upon the operating mode of the device. The “Clock Recovery Operations” ...
Page 67
... VCs received at the MT90520’s UTOPIA receive interface and then sent for processing by one of the RX_SARs. In order to keep statistics and other information (e.g., current state of the Correction/Detection state machine, last received sequence number) updated on a per-VC basis, the MT90520 employs two internal memories (one each for the UDT RX_SAR and the SDT RX_SAR) to hold Reassembly Control Structures ...
Page 68
... Within the SDT RX_SAR, there is an internal memory which is 16 Kwords long and 16-bits wide, to permit the setup of VCs of varying size and configuration. The MT90520 can handle up to 256 single-channel VCs (a full channels on each of the 8 ports). However, many other configurations with different “n” are also permissible. ...
Page 69
... All of the remaining fields within the SDT Reassembly Control Structure must be cleared to ‘0’ upon initialization. This ensures that the initialization, statistics, and status fields for the VC are configured to start with cleared values. MT90520 69 Zarlink Semiconductor Inc. ...
Page 70
... MT90520 Byte Add +00 Res Maximum Lead T +02 First Entry Last Entry +04 Structure Length Number of +06 CAS BS Res Channels V_RTS RTS Last Last +08 Fast State <3:1> <3:1> Seq Good PV_SN +0A I SDT RX_SAR Write Pointer <2:0> Current ...
Page 71
... AAL1 byte and determines whether the sequence number protection on the byte is correct by checking for CRC and parity errors. This state machine is primarily responsible for sending a corrected sequence number and CSI bit to the Fast Sequence Number Processing state machine (outlined in Section 4.6.1.4) for further sequence number processing. MT90520 71 Zarlink Semiconductor Inc. Data Sheet ...
Page 72
... The state machine examines the AAL1 byte and checks for CRC and parity errors, based on hard-wired values contained within the MT90520. The state machine then outputs two pieces of information for use by the Fast SN Processing state machine: a validity indicator and a sequence number. The validity signal indicates whether or not the received byte was determined to be valid (i ...
Page 73
... Table 15 - Operation of UDT Fast Sequence Number Processing State Machine MT90520 Action Taken - none - none - discard cell - discard cell - discard cell ...
Page 74
... Table 15 - Operation of UDT Fast Sequence Number Processing State Machine MT90520 Action Taken - UDT RX_SAR inserts a single dummy cell - accept received cell ...
Page 75
... Sequence number protection failure (looks like single cell loss) NOTE: D indicates the insertion of a dummy cell containing user-programmable data. Table 16 - Examples of Operation of the UDT Fast Sequence Number Processing State Machine MT90520 Action Taken - discard cell - accept received cell - declare lost_cell_error - per-port timeout circuitry is ...
Page 76
... Table 17 - Operation of SDT Fast Sequence Number Processing State Machine MT90520 Cells Used for Stream Reassembly ...
Page 77
... SDT pointer processing • extracting CAS from SDT cells and transferring it to the TDM module MT90520 - discard cell - discard cell (because misinserted cell was accepted when it shouldn’t have been) ...
Page 78
... Generally speaking, an “okay” condition means that the UDT RX_SAR is trying to write to a memory location which is within a distance of Maximum Lead from the TDM read pointer. Overflow conditions are conditions in which there is a risk of the UDT RX_SAR over-writing data which has yet to be read by the TDM MT90520 78 Zarlink Semiconductor Inc. ...
Page 79
... TDM and CAS data (if applicable) from SDT cells received at the UTOPIA interface to multiple SDT Reassembly Circular Buffers in external memory. In addition, SDT pointers must be analyzed to ensure that the extracted data is being directed to the correct TDM channels. MT90520 79 Zarlink Semiconductor Inc. ...
Page 80
... Pointer Reframes statistic field in the SDT Reassembly Control Structure is incremented the received pointer is not equal to 0, the misalignment between the internal controller and the received pointer is not resolved immediately: MT90520 80 Zarlink Semiconductor Inc. Data Sheet ...
Page 81
... Because there is no pre-defined mapping for the SDT Reassembly Circular Buffers, they can be programmed to start anywhere in the external memory for the MT90520 device (with some restrictions, explained here). The address of each SDT Reassembly Circular Buffer is formed as follows. A two-bit value is obtained from the CB_BASE_ADD field of the SDT Reassembly Control Register at byte-address 2040h ...
Page 82
... DS1 case; 16 consecutive entries in E1 case). • TDM Byte - This field contains the TDM data bytes which are extracted from received cells. If dummy cells have been inserted, this field contains the value of the dummy data programmed by the user. MT90520 Address to External Memory CAS TDM Byte ...
Page 83
... Reassembly Circular Buffer. However, if the user wants to send specific CPU-defined signalling out on a channel’s CSTo output, the user can put the desired data in the CASx fields of the control structure. Whatever data is present in the CASx fields is always transferred to external memory. MT90520 83 Zarlink Semiconductor Inc. ...
Page 84
... MT90520 device, due to concern about delay. Although CAS and TDM data are meant to be aligned, the MT90520 device would have to store up all of the data for an entire AAL1 structure (i.e., a complete multiframe) if the TDM data was to be output simultaneously with the corresponding CAS data. The resultant delay in the reception of data at the TDM ports is considered to be undesirable, so extra buffering of TDM data is not performed ...
Page 85
... Complete Reassembly Data Flow Overview The following figures give a top-level view of the data flow in the reassembly direction within the MT90520 device. Figure 30 shows the complete segmentation data path in UDT mode, from the incoming TDM data bus to the outgoing UTOPIA data bus, whereas Figure 31 shows the complete segmentation data path in SDT mode ...
Page 86
... The SDT RX_SAR and the UDT RX_SAR are responsible for generating data required for the performance of clock recovery operations within the MT90520. In the case of adaptive clock recovery, the active RX_SAR must generate a digital phaseword for transport to the internal per-port PLL. If SRTS clock recovery is being used, the RX_SAR extracts 4-bit RTS values from incoming ATM cells and sends them to the corresponding port’ ...
Page 87
... Stamps) carried in the CSI bits of received ATM cells. Each time an odd-sequence-numbered cell from a pre- selected VC arrives, the RX_SAR extracts the CSI bit from the AAL1 header byte for the cell and stores it. When the entire RTS nibble (4 bits) has been received transmitted to the Clock Management module of the MT90520 device. ...
Page 88
... Register at byte-address 3000h to set the Reassembly Cell Loss Integration Period. The value written in this field is used by each of the per-port timeout circuits in the MT90520 (i.e device-wide value and is not programmable on a per-port basis). The value within the field is expressed in terms of milliseconds and has a default value of 2.5 s. When any of the 8 per-port timeout counters reaches the timeout period without a cell arriving on the VC for the port, the CUT_VC_STATUS bit for the port is set in the port’ ...
Page 89
... Data RX_SAR. As such, the next cell (which may or may not actually be overwritten) should still be treated as corrupted. MT90520 89 Zarlink Semiconductor Inc. Data Sheet ...
Page 90
... SRTS clock recovery is provided as outlined in U.S. Patent No. 5,260,978. Although the CES specification indicates that SRTS is not required for SDT clock recovery, the MT90520 device permits the use of SRTS in the SDT mode of operation when not operating in the CAS sub-mode. In the reassembly direction, RTS values extracted from ...
Page 91
... Figure 32 - Functions of the Clock Management Module At a high level of abstraction, Figure 33 gives a general overview of the interaction between the Clock Management module and other modules within the MT90520 device. The internal configuration of the Clock Management module is examined more fully in the subsequent sub-module descriptions. ...
Page 92
... Both interfaces and the associated circuitry are shown in Figure 34 on page 94 and are explained more fully in the text which follows. MT90520 CLOCK MANAGEMENT MODULE CLOCK RECOVERY CLOCK CONTROL SUB-MODULE SUB-MODULE LOS_p STiCLK_p SToCLK_p F0 C4M/C2M 92 Zarlink Semiconductor Inc. Data Sheet MT90520 Device TDM Bus t Module e Clock r Logic ...
Page 93
... An additional function of the circuitry shown in Figure 34 is the generation of a common TDM line rate clock for use by all of the DS1/E1 ports of the MT90520 device when it is not in backplane mode. The user is able to select the source for this signal (labelled as common TDM rate clock in Figure 34) as coming from either an internal or an external reference ...
Page 94
... Note2: The SDT/UDT interface is replicated on a per-port basis. The backplane interface and common clock generation circuitry are only implemented once per device. Figure 34 - Interface to TDM Bus Module and Common Clock Generation Circuitry MT90520 SDT/UDT Interface (one Adaptive Mode 8 kHz Network Mode ...
Page 95
... As an alternative to the internal PLL, an external PLL may be used to provide a synchronous clock for transmission onto the TDM output bus. Using this method, a PRS-traceable signal from an external PLL is input to the MT90520 via the TDM_CLK pin. Since this is a “common” clock signal (i.e., one per device), TDM_CLK is routed to a multiplexer, as shown previously in Figure 34. The output of this multiplexer is a common clock which is routed to the clock selection multiplexers (one per port) in the “ ...
Page 96
... PLL output must be programmed to match the desired line rate. The line rate signal which is output from the external PLL is input to the MT90520 device at the TDM_CLK input pin. Alternatively, if the user does not wish to use an external PLL, the PRI_REF signal can be routed directly to the “ ...
Page 97
... Network Clock Divider Circuit This sub-module is implemented only once within the MT90520 device and is used by both the Transmit SRTS and Receive SRTS processes. The required circuitry is shown in Figure 38. The primary function of this sub-module is to create a divided-down network clock, fnxi, from a PHY rate clock (19 ...
Page 98
... In SDT mode, additional network clock rates are required because the size of the transmitted VCs can differ. The MT90520 permits RTS generation and SRTS clock recovery to be conducted on two different VC sizes (ranging from 32) for each device configuration. A secondary function of the network clock divider circuit is the generation of an internal 8 kHz clock signal from the 19 ...
Page 99
... RTS period (8 cells containing 47 payload bytes). Every time RTS_CLK pulses, the current value of the appropriate fnxi counter is stored in a FIFO. A value from the FIFO is transmitted to the TX_SAR cell header generator circuit once every 8-cell sequence. MT90520 Clock Management Module To port’s PLL for RX ...
Page 100
... The line rate clock (i.e., 2.048 MHz for DS1/E1/backplane) which is input to the MT90520 represents the rate at which bits are being received on a particular port. In SDT mode, the line rate only represents the bit rate the entire stream (e.g., 32 channels in ST-BUS mode) is transmitted in a single VC. ...
Page 101
... The Receive SRTS circuitry is quite simple, consisting only of a FIFO and a digital PLL, as seen in Figure 41. In addition, the Receive SRTS circuit makes use of signals generated within the Transmit SRTS circuitry, explained in Section 4.7.2.4. These pre-generated signals are also shown in Figure 41. MT90520 accumulator accumulator ...
Page 102
... Within the Clock Management module, the adaptive clock recovery technique is implemented via an internal PLL, as shown in Figure 42. Each port has its own PLL, which is the same as the one outlined for SRTS operation in the MT90520 Clock Management Module Digital PLL (refer FIFO_RTS< ...
Page 103
... Internal Digital PLL Sub-Module There is a separate Stratum 4 digital PLL for each of the 8 ports in the MT90520 device. This module takes care of generating several network clocks with the appropriate quality. The same PLL is used for clock recovery from TDM clocks, network clocks, SRTS data, or buffer pointer data in adaptive mode. ...
Page 104
... Note that the UDT RX_SAR and SDT RX_SAR Reassembly Control Structures must be configured appropriately if either Adaptive or SRTS Clock Recovery methods are to be used. For more details, refer to the UDT RX_SAR and SDT RX_SAR module descriptions in Section 4.6.1, “UDT RX_SAR and SDT RX_SAR Modules” earlier in this document. MT90520 Filter implemented in software (via CPU) Loop ...
Page 105
... The standards from Table 21 specify wander/jitter input tolerance and maximum output jitter. For the input wander/ jitter tolerance, the low frequency parts are the largest and are therefore the most important for the PLL requirements (see Table 22). With a corner frequency larger than 1.2 Hz, the PLL will follow wander below 0.1 Hz. MT90520 Frequency (MHz) Accuracy (ppm) 1 ...
Page 106
... The maximum intrinsic output jitter allowed on the output of the PLL is specified in ITU-T G.823/G.824 and is listed in Table 23. That said, the PLL within the MT90520 has a maximum intrinsic output jitter of one half of an MCLK cycle. However, any jitter on MCLK will be directly transferred to the output clocks. ...
Page 107
... Version<31:28>: Part Number<27:12>: Manufacturer ID<11:1>: 0001 0100 101 LSB<0>: Note that by mistake, two Zarlink products (MT90520 and MT90528) have been coded with the same Part Number into the JTAG Device ID Register. 4.8.3 Boundary Scan Instructions The TAP Controller of the MT90520 supports the following instructions: IDCODE, BYPASS, EXTEST, SAMPLE, HIGHZ, CLAMP ...
Page 108
... N, the number of least-significant VCI bits, and M, the number of least-significant VPI bits, (programmed by the user in the UNCB register) used to form the search addresses within the look-up table • maximum words MT90520 Notes Normal CPU access - writes and reads Buffer is 16 Kwords long Normal CPU access - writes and reads ...
Page 109
... VCs), and that minimum-sized Reassembly Circular Buffers are required. The size and location of the structures are programmable and do not necessarily have to be located at the addresses given in the example. The base address in the figure is the base address of external memory. MT90520 109 Zarlink Semiconductor Inc. ...
Page 110
... MT90520 Decimal Addressing (words) 0 UTOPIA Look-up Table 65,536 32 SDT Reassembly Circular Buffers for Port 0 98,304 32 SDT Reassembly Circular Buffers for Port 1 131,072 32 SDT Reassembly Circular Buffers for Port 2 163,840 294,911 294,912 32 SDT Reassembly Circular Buffers for Port 7 327,680 32 SDT Segmentation Circular Buffers for Port 0 ...
Page 111
... MT90520 Decimal Addressing (words) 0 UTOPIA Look-up Table 16 32 SDT Reassembly Circular Buffers for Port words 2064 32 SDT Reassembly Circular Buffers for Port words 4112 32 SDT Reassembly Circular Buffers for Port words 6160 14,351 14352 32 SDT Reassembly Circular Buffers for Port 7 ...
Page 112
... The first 512 Kbytes of address space are allocated for internal register use, while the latter half of address space contains internal memory blocks within the MT90520. As shown in Table 25 on page 113, the device does not implement all of the register space available inside the chip. The unused address space is reserved for future variants of the device ...
Page 113
... Low Address Word Indirection Register High Address Indirection Command Register Indirection Data Register Main Interrupt Enable Register MT90520 Revision Register TX_SAR Pointer Table Base Register Port 0 TX_SAR Pointer Table Base Register Port 1 TX_SAR Pointer Table Base Register Port 2 TX_SAR Pointer Table Base Register Port 3 ...
Page 114
... UVC_P4 4212 0000 UVP_P4 4214 0000 UVC_P5 MT90520 Description SDT Reassembly Service Enable Register SDT Reassembly Status Register SDT Reassembly Cell Counter Status Register SDT Reassembly Cell Counter Register MIB Timeout Configuration Register MIB Timeout Status Register 1 Timeout Configuration Register Port 0 ...
Page 115
... PLLEN_P4 Port 5 5250 0000 CCR_P5 5252 8000 CPAR_P5 MT90520 Description UDT VPI for Port 5 UDT VCI for Port 6 UDT VPI for Port 6 UDT VCI for Port 7 UDT VPI for Port 7 Clock Management Configuration Register External PLL Clock Source Register Clocking Configuration Register ...
Page 116
... TDM5_P2 622A 0000 TDM6_P2 Port 3 6230 0000 TDM1_P3 MT90520 Description Clocking DCO Difference Register SRTS FIFO Status Register PLL Enable Register Clocking Configuration Register Clocking Phase Accumulator Register Clocking DCO Difference Register SRTS FIFO Status Register PLL Enable Register ...
Page 117
... TDM6_P7 External Memory Interface Module 7000 0000 MACR 7004 0000 PERS MT90520 Description TDM Control Register 2 TDM Control Register 3 TDM Control Register 4 TDM Control Register 5 TDM Control Register 6 TDM Control Register 1 TDM Control Register 2 TDM Control Register 3 TDM Control Register 4 ...
Page 118
... Register Description Note: Unused bits (labeled as “Reserved”) are reserved for future use and although most of them are read-only (R/ O) bits, they should be written with ‘0’ to ensure software compatibility with future versions of the MT90520. 6.2.1 Microprocessor Interface Module Address: 0000 (Hex) ...
Page 119
... However, the CPU must wait for the ACC bit to be cleared before initiating the next access to another register block, internal memory, or external memory of the MT90520. Software cannot clear this bit (it can only be cleared by hardware). Access Cycle Complete Service Enable. ...
Page 120
... CPU Interrupt Enable. Always reads “0000_000”. Description MT90520 hardware revision. Table 32 - MT90520 Revision Register Description In SDT mode, these bits hold the base word address of the port p SDT Segmentation Pointer Table (see Figure 21 on page 59). In UDT mode, these bits form a pointer to the base word address of the UDT Segmentation Control Structure associated with port p ...
Page 121
... DTRP 6:0 R/O Reserved 15:7 R/O Table 36 - Data TX_SAR Read Pointer Register MT90520 Description Data TX_SAR Cell Buffer Size. This field indicates the number of non-CBR data cells which can be held in the Data TX_SAR’s Cell Buffer: “00” cells “01” cells “10” cells “ ...
Page 122
... R/O Reserved 15:1 R/O Table 39 - Data TX_SAR Status Register MT90520 Description Data TX_SAR Enable. When cleared, the Data TX_SAR Read Pointer (register at 103Ch) is reset to “000_0000” and no data cells are transmitted. When set, the Data TX_SAR sends the cells stored in the Data TX_SAR Cell Buffer. ...
Page 123
... UDT_LOST_ 3 R/W ROLL_SE Table 42 - UDT Reassembly Service Enable Register MT90520 Description When cleared, the TX_SAR will not produce UDT or SDT cells for any port. Always reads “0000_0000_0000_000”. Description UDT RX_SAR Dummy Cell Octet. This octet is inserted into a port’s UDT Reassembly Circular Buffer 47 times when dummy cell insertion is required ...
Page 124
... Position CELL_COUNTER 15:0 R/O Table 44 - UDT Reassembly Cell Counter Register MT90520 Description When set, the assertion of the Misinserted Cells Counter Rollover status bit in a UDT Reassembly Control Structure will cause the UDT_RXSAR_STATUS bit to be set in the UDT Reassembly Status Register at 2004h. When set, the assertion of the Buffer Underrun Counter Rollover status bit in a UDT Reassembly Control Structure will cause the UDT_RXSAR_STATUS bit to be set in the UDT Reassembly Status Register at 2004h ...
Page 125
... R/O/L Reserved 15:5 R/O Table 46 - Data RX_SAR Status Register MT90520 Description Data RX_SAR Enable. When cleared, the Data RX_SAR Write Pointer (DRWP at 2026h) is reset to 00h and all received data cells are ignored. When set, received data cells are processed normally. Default of ‘0’ means that the Data RX_SAR is usually disabled. ...
Page 126
... Note: The write pointer value is cleared to “00h” upon start-up and each time that the DRENB bit is cleared (i.e., when the Data RX_SAR is disabled, the write pointer is automatically cleared to “00h”). Table 48 - Data RX_SAR Write Pointer Register MT90520 Description Data RX_SAR Cell Buffer Size. ...
Page 127
... R/W Reserved 15:11 R/O Table 51 - SDT Reassembly Control Register MT90520 Description Data RX_SAR Cell Buffer Read Pointer. Indicates the cell structure number which is currently being read by the CPU. This value should not be incremented by the CPU at the end of a cell-read; therefore read operation is not in progress, the pointer indicates the cell location which was last read by the microprocessor. Always reads “ ...
Page 128
... SE Reserved 15:11 R/O Table 52 - SDT Reassembly Service Enable Register MT90520 Description When set, the assertion of the Reassembled Cells Counter Rollover status bit in an SDT Reassembly Control Structure will cause the SDT_RXSAR_STATUS bit to be set in the SDT Reassembly Status Register at 2044h. When set, the assertion of the AAL1 Header Byte Error Counter Rollover status bit in an SDT Reassembly Control Structure will cause the SDT_RXSAR_STATUS bit to be set in the SDT Reassembly Status Register at 2044h ...
Page 129
... Position CELL_COUNTER 15:0 R/O Table 55 - SDT Reassembly Cell Counter Register MT90520 Description Base word address of the last SDT Reassembly Control Structure to generate a serviceable event (i.e., a status field rollover or bit setting). This field is cleared when the SDT_RXSAR_STATUS bit in this register is cleared. SDT RX_SAR Service Enable. ...
Page 130
... R/O Reserved 15:8 R/O MT90520 Reassembly Cell Loss Integration Period. If cells are continuously lost for this period of time (given in ms), the CUT_VC_STATUS bit is set in the Timeout Configuration Register (3200h + p*2h) corresponding to the VC’s “VC TDM Port”. Default value = 2 set, indicates that either an unmasked late cell event or an unmasked cut VC event has occurred on port 0 ...
Page 131
... R/W UTO_CLK_SEL 2 R/W Table 59 - UTOPIA Configuration Register MT90520 Description Late Cell Timeout cell has not been received prior to this timeout (measured in 125 µs increments), an internal flag is set, indicating a late cell arrival. This timer should generally be set to a value equal to the cell assembly time, plus the expected CDV. Default: 256 ms In UDT mode, if this timeout period is passed, the LATE_CELL_STATUS bit in this per-port register will be set ...
Page 132
... ATM Forum UTOPIA Level 2 specification. PHY/ATM. When set, the MT90520’s UTOPIA interface will operate in PHY mode; when the bit is cleared, the MT90520’s UTOPIA interface will operate in ATM mode. Defines the address of the MT90520 device used to compare to the UTO_IN_ADD and UTO_OUT_ADD buses when operating in MPHY mode ...
Page 133
... R/W Reserved 15:12 R/O MT90520 Description Contains the 16 most significant bits of the Look-Up Table base address. These bits represent byte address bits<20:5> of the external memory. If N+M is greater than 4, bits<(N+M):5> of the Look-Up Table base address should be set to 0. (For example, if N+M=7, bits<7:5> should be set to “000”) Description Contains match values for each of the bits in the VCI ...
Page 134
... Reserved 15:7 R/O Table 67 - UTOPIA FIFO Status Register MT90520 Description Each bit, when set, enables the comparison of a cell’s VPI and the corresponding VP_MATCH bit bit in this register is not set, the corresponding bit in the received cell VPI is considered valid, regardless of the setting in the VP_MATCH field. In UNI mode, bits< ...
Page 135
... Position UDT_VCI 15:0 R/W Table 71 - UDT VCI for Port p (one per port) MT90520 Description If set, this status bit indicates that the UTOPIA interface has received 2 by the UTOPIA Incoming Cell Counter at 4016h. If set, this status bit indicates that the UTOPIA interface has received 2 containing parity errors, as counted by the UTOPIA Parity Mismatches Register at 400Eh. Always reads “ ...
Page 136
... External/Internal. When set, the common clock and the “master” C4M_C2M and F0 signals are generated from the clock input to the MT90520 at TDM_CLK (this is usually sourced from an external PLL). When cleared and if in master mode, the C4M_C2M and F0 signals are generated from an internal version of the output signal PRI_REF ...
Page 137
... Note 2: Since RTS support is only provided in SDT mode for VCs carrying channels, FNXI rates of 4.86 MHz and 9.72 MHz should not be used. Table 73 - Clock Management Configuration Register MT90520 Description FNXI Rate Selector 1. (See Notes 1 and 2) These bits are used to select the rate of the FNXI clock (#1) from which outgoing RTS values will be generated, and to which incoming RTS values will be compared: “ ...
Page 138
... R/W Reserved 15:12 R/O Table 74 - External PLL Clock Source Register MT90520 Description Primary Clock Source for External PLL. Used to select the primary clock source for the external PLL (signals output on PRI_REF and PRI_LOS). Bits<4:0> indicate which port should provide the clock source (only “00000”:“00111” ...
Page 139
... R/W PLL_MODE_SEL 8:7 R/W Table 75 - Clocking Configuration Register (one per port) MT90520 Description SToCLK Selector. These bits are used to select the source for the port’s SToCLK output signal: “00” = MCLK/2 “01” = STiCLK “10” = PLLCLK (generated by the port’s internal PLL) “ ...
Page 140
... Note: The reset value of this register can only be read as 8000h if the corresponding PLL is disabled (bit<0> cleared in the PLL Enable Register, located at address 5208h+p*10h). Table 76 - Clocking Phase Accumulator Register (one per port) MT90520 Description PLL input mode. These bits define the input used to generate the PLL’s output clock. ...
Page 141
... PLL_ENABLE 0 Reserved 15:1 Table 79 - PLL Enable Register (one per port) MT90520 Description Frequency offset value. When PLL_MODE_SEL (in register 5200h + p*10h) is set to CPU mode, the value in this field is used to set the PLL output frequency directly, instead of using the filter output. In CPU mode, the PLL input selected by PLL_INPUT_SEL (in register 5200h + p*10h longer used. Data read from this field is interpreted as 2’ ...
Page 142
... Incoming Loss of Signal. (Applies only to UDT mode.) ‘0’ = Normal operation (continue to use STiCLK during an LOS condition). ‘1’ = Switch to MT90520’s internal clock source if loss of signal is detected on CSTi/LOSi. Incoming TDM LOS Polarity. (Applies only to UDT mode; must be set in SDT mode.) ‘ ...
Page 143
... FORMAT TDM_LOW_ 15 R/W LATENCY_LPBK Table 82 - TDM Control Register 1 (one per port) MT90520 Description TDM Frame Pulse Selection. (Applies only to SDT mode.) ‘0’ = STiMF pin is a frame pulse. ‘1’ = STiMF pin is a multiframe pulse. In Backplane SDT mode, this bit must cleared. ...
Page 144
... Always reads “0000”. Segmentation TDM Port Control. ‘0’ = Port is not active (data is not transferred from the TDM module to the rest of the MT90520). ‘1’ = Port is active. Segmentation Internal Enable Process. ‘0’ = Process is disabled. ‘1’ = Process that writes data/CAS to the TDM input buffer is enabled. ...
Page 145
... PERM_ 15:0 R/O/L UNDERRUN_ REPORT Table 86 - TDM Control Register 5 (one per port) MT90520 Description Always reads ‘0’. UDT Loss of Signal (LOS) Service Enable. When this bit is set and UDT_LOS_STATUS is asserted, TDM_SRV is set in the Main Status Register at 0002h. UDT TDM Output Buffer Error Service Enable. ...
Page 146
... Label Type Position LBPRTY_E 0 R/O/L MT90520 Description Permanent Underrun Report. (Applies only to SDT mode.) This register represents bits<15:0> of the 32-bit permanent underrun reports. Bit<15> corresponds to channel 15, bit<14> corresponds to channel 14, etc. When an underrun occurs on a certain channel, the corresponding bit is set high; the microprocessor can clear these bits by writing them to ‘ ...
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... R/O/L Reserved 15:2 R/O Table 89 - Parity Error Status Register MT90520 Description High Byte Parity Error. If set, this bit indicates that a parity error has occurred in the high 8 bits of the data word being read from external memory. A parity error may occur if a location in memory is read before being written. Writing ‘0’ to this bit clears it. ...
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... Device Power Dissipation (2.5 V and 3.3 V supplies) 7 Input High Voltage (3.3 V CMOS) 8 Input Low Voltage (3.3 V CMOS) 9 Switching Threshold (3.3 V CMOS) 10 Schmitt Trigger Positive Threshold 11 Schmitt Trigger Negative Threshold MT90520 Symbol V DD2 V DD3 unless otherwise stated. Long-term exposure to absolute maximum ratings may affect ...
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... AAL1 cells, giving Look-Up Table reads of 1 800 reads/second. Note 3: SDT mode supply current and device power includes 1800 cells of CPU/OAM traffic in both directions, and sufficient discards of non-AAL1 cells to bring Look-Up Table reads to 1 000 000 reads/second. MT90520 a Sym. Min. Typ. ...
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... Note 2: Both CS and RD must be asserted for a read cycle to occur. A read cycle is completed when either de-asserted. Note 3: There should be a minimum of 3 MCLK periods between CPU accesses, to allow the MT90520 to recognize the accesses as separate (i.e., CS must be de-asserted for 3 MCLK cycles between CPU accesses). ...
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... ADDS CPU_ADD[20:1] AEM t RACC RDY t RRDYL CPU_DATA[15:0] Figure 47 - Intel CPU Interface Timing - Read Access MT90520 ADDRESS VALID t DS DATA VALID 151 Zarlink Semiconductor Inc. Data Sheet ADDH RRDYZ ...
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... Note 2: Both CS and WR must be asserted for a write cycle to occur. A write cycle is completed when either de-asserted. Note 3: There should be a minimum of 3 MCLK periods between CPU accesses, to allow the MT90520 to recognize the accesses as separate (i.e., CS must be de-asserted for 3 MCLK cycles between CPU accesses). ...
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... RDTKH DTACK t ADDS CPU_ADD[20:1] AEM R_W CPU_DATA[15:0] Figure 49 - Motorola CPU Interface Timing - Read Access MT90520 t RACC ADDRESS VALID t DS 153 Zarlink Semiconductor Inc. Data Sheet RDTKZ ADDH ADDH DATA VALID TT ...
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... Note 2: Both CS and DS must be asserted for a write cycle to occur. A write cycle is completed when either de-asserted. Note 3: There should be a minimum of 3 MCLK periods between CPU accesses (CS de-asserted), to allow the MT90520 to recognize the accesses as separate (i.e., CS must be de-asserted for 3 MCLK cycles between CPU accesses). ...
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... VALID and (MEM_CS_X and MEM_WR) asserted) Table 92 - External Memory Interface Timing - Read Cycle Parameters MCLK MEM_ADD[19:0] ADDRESS1 VALID MEM_CS_X t OD MEM_WR MEM_DATA[17:0] (flow-through) MEM_DATA[17:0] (pipelined) Figure 51 - External Memory Interface Timing - Read Cycle MT90520 Sym. Min. Typ. Max DIS t 2 DIH ...
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... Drive to High-Z Time - MCLK rising to MEM_DATA[17:0] High-Z Table 93 - External Memory Interface Timing - Write Cycle Parameters MCLK MEM_ADD[19: MEM_CS_X MEM_WR t OD MEM_DATA[17:0] (flow-through) MEM_DATA[17:0] (pipelined) Figure 52 - External Memory Interface Timing - Write Cycle MT90520 Sym. Min. Typ. Max ...
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... The frame pulse can have either positive or negative polarity. Figure 55 - Nominal SDT Mode Timing Diagram - Generic DS1 (1.544 Mbps) Table 94 and Table 95 refer to input clock parameters which are displayed in Figure 56 and Figure 57, which follow the tables. MT90520 Bit n-1 Bit n Bit 0 ...
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... Data Hold Time - STiCLK/C4M/C2M falling to DSTi/CSTi INVALID Sampling on falling edge Data Setup Time - DSTi/CSTi VALID to STiCLK/C4M/C2M rising Sampling on rising edge Data Hold Time - STiCLK/C4M/C2M rising to DSTi/CSTi INVALID Sampling on rising edge Table 95 - TDM Bus Input Data Parameters MT90520 Sym. Min. Typ. Max. t STiCK ...
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... Mbps bus (4.096 MHz clock) SToCLK/C4M/C2M Pulse Width (HIGH / LOW) 1.544 Mbps bus (1.544 MHz clock) 1.544 or 2.048 Mbps bus (2.048 MHz clock) 2.048 Mbps bus (4.096 MHz clock) Table 96 - TDM Bus Output Clock Parameters MT90520 t t FIS FIH t STiCK ...
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... Note: In Generic format, both clock polarity and pulse polarity are programmable. Data can be driven out either on the falling edge or the rising edge of the clock. The frame pulse can have either positive or negative polarity. Figure 58 - TDM Bus Output Clocking Parameters - Generic MT90520 Sym. Min. ...
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... INVALID and UTO_IN_SOC and UTO_IN_CLAVATM_ENBPHY de-asserted) Output Delay - UTO_IN_CLK rising to UTO_IN_ENBATM_CLAVPHY asserted Output Hold Time - UTO_IN_CLK rising to UTO_IN_ENBATM_CLAVPHY de-asserted Note: The MT90520 operates with the UTOPIA cell-level handshake. Table 98 - UTOPIA Level 1 Interface Timing - ATM mode - Incoming Data (UTOPIA RX Bus) MT90520 t SODV Bit 6, Channel 0 ...
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... Output Delay - UTO_OUT_CLK rising to (UTO_OUT_DATA[7:0] VALID and UTO_OUT_ENBATM_CLAVPHY and UTO_OUT_SOC asserted) Output Hold Time - UTO_OUT_CLK rising to (UTO_OUT_DATA[7:0] INVALID and UTO_OUT_ENBATM_CLAVPHY and UTO_OUT_SOC de-asserted) Table 99 - UTOPIA Level 1 Interface Timing - ATM mode - Outgoing Data (UTOPIA TX Bus) MT90520 t t URXH t URXIH t t URXIS URXIH ...
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... INVALID and UTO_IN_SOC, UTO_IN_CLAVATM_ENBPHY de-asserted) Output Delay - UTO_IN_CLK rising to UTO_IN_ENBATM_CLAVPHY asserted Output Hold Time - UTO_IN_CLK rising to UTO_IN_ENBATM_CLAVPHY de-asserted Table 100 - UTOPIA Level 1 Interface Timing - PHY mode - Incoming Data (UTOPIA TX Bus) MT90520 t UTX1L at least 4 cycles before the next cell H3 H2 P44 ...
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... VALID and UTO_OUT_ENBATM_CLAVPHY and UTO_OUT_SOC asserted) Output Hold Time - UTO_OUT_CLK rising to (UTO_OUT_DATA[7:0] INVALID and UTO_OUT_ENBATM_CLAVPHY and UTO_OUT_SOC de-asserted) Table 101 - UTOPIA Level 1 Interface Timing - PHY mode - Outgoing Data (UTOPIA RX Bus) MT90520 t UTX1H P46 H2 H3 P44 P45 4 cycles before the next cell Sym ...
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... Since the MT90520 does not support multi-PHY (MPHY) operation in ATM mode, the Level 2 ATM timing diagrams are identical to the ones for Level 1 operation, except that in Level 2, the MT90520 features a 16-bit data bus in both the TX and RX directions and it supports load at 33 MHz and MHz. Note that the address bus is only used when in PHY mode ...
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... See Note 2 UTO_IN_SOC Note the address of the MT90520 the address of another PHY device, where N is not equal address of 1Fh (31d) indicates a null PHY port. Note 2: UTO_IN_DATA is a 16-bit bus; therefore, P24 indicates the last cell payload word to be transmitted. ...
Page 167
... See Note 2 UTO_OUT_SOC Note the address of the MT90520 the address of another PHY device, where N is not equal address of 1Fh (31d) indicates a null PHY port. Note 2: UTO_OUT_DATA is a 16-bit bus; therefore, P24 indicates the last cell payload word to be transmitted. ...
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... External Memory Interface Connections The MT90520 can interface with both the pipelined and flow-through types of synchronous static zero bus turnaround (ZBT) RAM. The clock driving the external memory device must be the same as the clock which is fed to the MT90520 at its MCLK input, as shown in Figure 67 below. ...
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... UTOPIA Interface Connections The following table lists all of the signals on the UTOPIA interface of the MT90520. In addition, it indicates what the pin corresponds to in terms of the functionality of the UTOPIA standard, depending on the mode of operation of the UTOPIA interface. MT90520 MT90520 Signal Name Signal Direction ...
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... TxSOC TxPrty PHY Device Note 1: The MT90520 does not have to drive the UTOPIA clock. The UTO_IN_CLK and UTO_OUT_CLK pins of the MT90520 can either be inputs or outputs. Note 2: When in ATM mode, UTO_IN_CLAVATM_ENBPHY, UTO_IN_SOC, UTO_OUT_CLAVATM_ENBPHY and UTO_OUT_SOC should be pulled down also recommended to pull up UTO_IN_ENBATM_CLAVPHY and UTO_OUT_ENBATM_CLAVPHY ...
Page 171
... ATM Device Note 1: The ATM device is not required to drive the UTOPIA clock. The UTO_IN_CLK and UTO_OUT_CLK pins of the MT90520 can either be inputs or outputs. Note 2: When in PHY mode, UTO_IN_ENBATM_CLAVPHY, UTO_IN_SOC, UTO_OUT_ENBATM_CLAVPHY and UTO_OUT_SOC should be pulled down also recommended to pull up UTO_IN_CLAVATM_ENBPHY and UTO_OUT_CLAVATM_ENBPHY ...
Page 172
... Some components of the latency are a function of the MT90520 architecture, which has been designed to minimize this latency. Finally, some components are externally determined, such as the physical layer and network delays, and network Cell Delay Variation (CDV) which must be compensated for in the CDV buffering ...
Page 173
... UTOPIA bus, and queuing delays at the switches through the network, including queuing in front of the physical layer devices directly connected to the MT90520. This is in general a variable delay, and usually represents the largest source of Cell Delay Variation (CDV) that the reassembly path (RX_SAR) has to deal with ...
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... RX end on the same TDM channel number as it was sampled in at the TX end. For example, if the TDM byte comes into the segmentation end on TDM channel driven out at the reassembly end on TDM channel 3. MT90520 Total Static RX / Reassembly (µsec) 1 ...
Page 175
... Broadband Network,” United States Patent 5,260,978, Nov. 1993. Note: Telcordia (formerly Bellcore) asserts that its U.S. Patent No. 5,260,978 for Synchronous Residual Timestamp (SRTS) Timing Recovery in a Broadband Network may apply to the ATM Adaptation Layer Type 1 (AAL1) ANSI Standard (T1.630-1993) referenced in Section 3.4 of af-vtoa-0078.000. MT90520 175 Zarlink Semiconductor Inc. Data Sheet ...
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... OAM - Operations, Administration and Maintenance; MSB within the PTI field of the ATM cell header which indicates if the ATM cell carries management information such as fault indications. PHY - Physical Layer; bottom layer of the ATM Reference Model; provides ATM cell transmission over the physical interfaces that interconnect the various ATM devices. MT90520 176 Zarlink Semiconductor Inc. Data Sheet ...
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... VPI - Virtual Path Identifier; 8-bit value (in UNI; 12 bits in NNI) in the ATM cell header that indicates the virtual path (VP) to which a cell belongs. VTOA - Voice and Telephony over ATM; intended to provide voice connectivity to the desktop, and to provide interoperability with existing N-ISDN and PBX services. MT90520 177 Zarlink Semiconductor Inc. Data Sheet ...
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... ZBT and Zero Bus Turnaround are trademarks held by Integrated Device Technology Inc. 10.1 Glossary References: The ATM Glossary - ATM Year 97 - Version 2.1, March 1997 The ATM Forum Glossary - May 1997 Zarlink Semiconductor Glossary of Telecommunications Terms - May 1995. MT90520 178 Zarlink Semiconductor Inc. Data Sheet ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...