mt90520 Zarlink Semiconductor, mt90520 Datasheet - Page 136

• Manufacturer Part Number: mt90520
• Description: 8-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

6.2.8
Address: 5000 (Hex)
Label: CMCR
Reset Value: 0001 (Hex)
Address: 4202 + p*4 (Hex)
Label: UVP_Pp (where p represents the port number)
Reset Value: 0000 (Hex)
SLV_N_MSTR
8_KHZ_SEL
EXT_N_INT
OAM_SEL
F0_MODE
UDT_VPI
Reserved
Label
Label
Clock Management Module
Position
Position
15:13
11:0
Bit
12
Bit
4:2
0
1
5
Table 73 - Clock Management Configuration Register
Type
R/W
R/W
R/O
Type
R/W
R/W
R/W
R/W
Table 72 - UDT VPI for Port p (one per port)
UDT VPI for TDM port p.
The VPI value of the incoming cell is compared to this value to determine if the cell is
destined for port p. In UNI mode, only the 8 least significant bits of this field are used for
the comparison. In NNI mode, all 12 bits are used.
OAM select for port p.
When set, OAM cells with matching VPI/VCI are sent to the Receive Data Cell Buffer.
When cleared, OAM cells arriving on this VC are discarded.
Always reads “000”.
Slave/Master.
When set, the signals F0 and C4M_C2M are sourced from the TDM backplane (inputs).
When cleared, the MT90520 generates these signals (outputs).
When the MT90520 is not operating in backplane mode, this bit should be set to 1
(i.e., slave mode). Furthermore, if operating in backplane mode, this bit should
only be cleared if the user wishes the MT90520 to control the F0 and C4M_C2M
backplane signals.
External/Internal.
When set, the common clock and the “master” C4M_C2M and F0 signals are generated
from the clock input to the MT90520 at TDM_CLK (this is usually sourced from an external
PLL).
When cleared and if in master mode, the C4M_C2M and F0 signals are generated from an
internal version of the output signal PRI_REF.
Frame Pulse Format Selector.
F0_MODE<0> - Frame Pulse Polarity (used only in Generic mode):
F0_MODE<1> - Frame Pulse Trigger Edge (used only in Generic mode):
F0_MODE<2> - Frame Pulse Format:
Internal 8 kHz clock source.
Used to select the origin of the 8 kHz clock source used by the internal PLLs.
When set, the 8 kHz clock is generated as a divided-down version of the 19.44 MHz clock
input to the MT90520 at PHY_CLK.
When cleared, an 8 kHz clock is expected to be input directly at PHY_CLK.
‘0’ = Negative polarity
‘1’ = Positive polarity.
‘0’ = Negative-edge trigger
‘1’ = Positive-edge trigger.
‘0’ = Generic
‘1’ = ST-BUS.
Zarlink Semiconductor Inc.
MT90520
136
Description
Description
Data Sheet