mt90520 Zarlink Semiconductor, mt90520 Datasheet - Page 8

• Manufacturer Part Number: mt90520
• Description: 8-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

MT90520
Data Sheet
List of Figures
Figure 49 - Motorola CPU Interface Timing - Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 50 - Motorola CPU Interface Timing - Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 51 - External Memory Interface Timing - Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 52 - External Memory Interface Timing - Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 53 - Nominal UDT Mode Timing Diagram - DS1 (1.544 Mbps) and E1 (2.048 Mbps) . . . . . . . . . . . . . . . 157
Figure 54 - Nominal SDT Mode Timing Diagram - Generic and ST-BUS DS1 or E1 (2.048 Mbps). . . . . . . . . . . 157
Figure 55 - Nominal SDT Mode Timing Diagram - Generic DS1 (1.544 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Figure 56 - TDM Bus Inputs - Generic Bus Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 57 - TDM Bus Inputs - ST-BUS Sampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 58 - TDM Bus Output Clocking Parameters - Generic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 59 - TDM Bus Output Clocking Parameters - ST-BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 60 - TDM Bus Outputs - Serial Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 61 - TDM Bus Outputs - Serial Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 62 - UTOPIA Level 1 Interface Timing - ATM Mode - Outgoing Data (UTOPIA TX Bus) . . . . . . . . . . . . . 163
Figure 63 - UTOPIA Level 1 Interface Timing - PHY Mode - Incoming Data (UTOPIA TX Bus) . . . . . . . . . . . . . 164
Figure 64 - UTOPIA Level 1 Interface Timing - PHY Mode - Outgoing Data (UTOPIA RX Bus) . . . . . . . . . . . . 165
Figure 65 - UTOPIA Level 2 Interface Timing - PHY Mode - Incoming Data (UTOPIA TX Bus) . . . . . . . . . . . . . 166
Figure 66 - UTOPIA Level 2 Interface Timing - PHY Mode - Outgoing Data (UTOPIA RX Bus) . . . . . . . . . . . . . 167
Figure 67 - External Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 68 - ATM Mode: External UTOPIA Pin Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 69 - PHY Mode: External UTOPIA Pin Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
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