am79c974 Advanced Micro Devices, am79c974 Datasheet - Page 77

• Manufacturer Part Number: am79c974
• Description: Pcnettm-scsi Combination Ethernet And Scsi Controller For Pci Systems
• Manufacturer: Advanced Micro Devices

Logic block via a 32-bit data bus, and the funnel logic
properly reduces this stream of data to a 16-bit stream to
SCSI DMA Programming Sequence
The following section outlines the procedure for execut-
ing SCSI DMA operations:
1. Issue IDLE command to the DMA Engine
2. Configure the SCSI block registers (e.g. synchro-
3. Program the DMA registers to set up address and
4. Issue a transfer command to the SCSI command
5. Issue the START command to the DMA engine
6. At the end of the DMA transaction, issue the IDLE
Memory Descriptor List (MDL) Based DMA
Programming
The following section outlines the use of the MDL for
Register Acronym
CMD
STC
SPA
WBC
WAC
STATUS
SMDLA
WMAC
nous operation, offset values, etc.)
transfer count
registers
command to the DMA engine
DMA FIFO
Addr (Hex)
96-Byte
(B)+4C
(B)+5C
(B)+40
(B)+44
(B)+48
(B)+50
(B)+54
(B)+58
Figure 26. DMA FIFO to SCSI FIFO Interface
Register Description
Command
Starting Transfer Count
Starting Physical Address
Working Byte Counter
Working Address Counter
Status Register
Starting Memory Descriptor List (MDL) Address
Working MDL Counter
32
Table 6. The DMA Registers
P R E L I M I N A R Y
(bits 31:8 reserved, bits 7:0 used)
Am79C974
(bits 31:8 reserved, bits 7:0 used)
Funnel
Logic
properly interface with the SCSI FIFO.
scatter-gather DMA operations:
1. Set up the MDL list
2. Use the programming sequence defined earlier for
DMA Registers
The following is a summary of the DMA register set or
the DMA Channel Context Block (DMA CCB). These
registers control the specifics for DMA operations such
as transfer length and scatter-gather options. The three
read-only working counter registers allow the system
software and driver to monitor the DMA transaction.
Each register address is represented by the PCI Con-
figuration Base Address (B) and its corresponding offset
value. The Base address for the SCSI controller is
stored at register address (10h) in the SCSI PCI configu-
ration space.
(bits 31:24 reserved, bits 23:0 used)
(bits 31:0 used)
(bits 31:0 used)
initiating a SCSI DMA transfer
16
SCSI FIFO
16-Byte
18681A-30
AMD
Type
R/W
R/W
R/W
R/W
R
R
R
R
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