am79c974 Advanced Micro Devices, am79c974 Datasheet - Page 78

• Manufacturer Part Number: am79c974
• Description: Pcnettm-scsi Combination Ethernet And Scsi Controller For Pci Systems
• Manufacturer: Advanced Micro Devices

Command Register (CMD)
The upper 3 bytes of Command register are reserved,
the remaining (LSB) byte is defined as follows:
Address (B)+40h, LSB
DIR:
Data transfer direction bit. When this bit is set, the direc-
tion of transfer is from SCSI to memory.
INTE_D:
DMA transfer active interrupt enable bit. When this bit is
DMA Scatter-Gather Mechanism
The Am79C974 controller contains a scatter-gather
translation mechanism which facilitates faster data
transfers. This feature uses a Memory Descriptor List
which is stored in system memory. Use of the Memory
Descriptor List allows a single SCSI transfer to be read
from (or written to) non-contiguous physical memory lo-
cations. This mechanism avoids copying the transfer
data and MDL list, which was previously required for
conventional DMA operations.
Memory Descriptor List (MDL)
The MDL is a non-terminated (no End Of File marker)
list of 32-bit page frame addresses, which is always
aligned on a Double Word boundary. The format is
shown below:
31
DMA Scatter-Gather Operation
(4k aligned elements)
The scatter-gather mechanism described below
78
Page Frame Address
DIR
7
CMD1
AMD
0
0
1
1
INTE_D
6
INTE_P
CMD0
5
0
1
0
1
MDL
4
Reserved Reserved
Command
3
ABORT
START
BLAST
IDLE
12 11
2
READ/WRITE
Ignored
Description
Resets the DMA block to the IDLE state. Stops any current transfer. Does not
affect status bits or cause an interrupt.
Empties all data bytes in DMA FIFO to memory during a DMA
write operation. Upon completion, the ‘BCMPLT’ bit will be set
in the DMA Status register. This command should not be used
during a DMA read operation.
Terminates the current DMA transfer. Restores the DMA engine to the IDLE
state. Sets the ABORT bit (bit 2) in the status register.
Note: This is only valid after a ‘START’ command is issued.
Initiates a new DMA transfer. These bits must remain set
throughout the DMA operation until the ‘DONE’ bit in the DMA
Status Register is set.
Note: This command should be issued only after all other
control bits have been initialized.
CMD1
1
P R E L I M I N A R Y
CMD0
0
Am79C974
0
set, the ERROR or DONE condition will cause INTA to
be asserted.
INTE_P:
Page transfer active interrupt bit.
MDL:
Memory Descriptor List (MDL) SPA enable bit.
RESERVED:
Reserved for future expansion. The zero value must be
written in these bits.
CMD1-0:
These two bits are encoded to represent four com-
mands: IDLE, BLAST, START, and ABORT.
assumes 4k page alignment and size for all MDL entries
except the first and last entry. This feature is enabled by
setting the MDL bit in the DMA Command register (Bit 4,
Address (B)+40h).
1. a) Prepare the Memory Descriptor List (MDL)
Note: The value in the SMDLA register must be double
word aligned. Therefore, read/write transactions will al-
ways begin on a double word boundary.
b) Load the address of the starting entry in the
c) Program the Starting Transfer Count (STC)
through software and store it in system
memory.
Memory Descriptor List (MDL) into the Start
Memory Descriptor List Address (SMDLA)
register. This value is automatically copied into
the Working MDL Address Counter (WMAC).
register with the total transfer length (i.e., # of
bytes). Also program the Starting Physical
Address (SPA) register (bits 11:0) with the
starting offset of the first entry.