am79c940 Advanced Micro Devices, am79c940 Datasheet - Page 31

• Manufacturer Part Number: am79c940
• Description: Media Access Controller For Ethernet Mace
• Manufacturer: Advanced Micro Devices

(f) When neither BE0 nor BE1 are asserted, no data
BIU to Control and Status
Register Data Path
All registers in the address range 2–31 are 8-bits wide.
When a read cycle is executed on any of these registers,
the MACE device will drive data on both bytes of the
data bus, regardless of the programming of BSWP.
When a write cycle is executed, the MACE device
strobes in data based on the programming of BSWP as
shown in the tables below. All accesses to addresses
2–31 are independent of the BE
BE0
BE0
BE0
BE0
Byte Alignment For Register Read Operations
Byte Alignment For Register Write Operations
X
X
X
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
transfer will take place. DTV will not be asserted.
Byte Alignment For FIFO Read Operations
Byte Alignment For FIFO Write Operations
BE1
BE1
BE1
BE1
X
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
BSWP
BSWP
BSWP
BSWP
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
1
DBUS7–0
DBUS7–0
DBUS7–0
DBUS7–0
0
Read
Read
Write
Data
Data
Data
and BE
n+1
n+1
X
X
X
X
X
X
X
n
n
n
n
n
n
n
n
1
DBUS15–8
DBUS15–8
DBUS15–8
DBUS15–8
pins.
Read
Read
Write
n+1
n+1
Data
Data
Data
X
X
X
X
X
X
X
n
n
n
n
n
n
n
n
Am79C940
FIFO Sub-System
The MACE device has two independent FIFOs, with
128-bytes for receive and 136-bytes for transmit opera-
tions. The FIFO sub-system contains both the FIFOs,
and the control logic to handle normal and exception re-
lated conditions.
The Transmit and Receive FIFOs interface on the net-
work side with the serializer/de-serializer in the MAC en-
gine. The BIU provides access between the FIFOs and
the host system to enable the movement of data to and
from the network.
Internally, the FIFOs appear to the BIU as independent
16-bit wide registers. Bytes or words can be written to
the Transmit FIFO (XMTFIFO), or read from the Re-
ceive FIFO (RCVFIFO). Byte and word transfers can be
mixed in any order. The BIU will ensure correct byte or-
dering dependent on the target host system, as deter-
mined by the programming of the BSWP bit in the BIU
Configuration Control register.
The XMTFIFO and RCVFIFO have three different
modes of operation. These are Normal (Default), Burst
and Low Latency Receive. Default operation will be
used after the hardware RESET pin or software SWRST
bit have been activated. The remainder of this general
description applies to all modes except where specific
differences are noted.
Transmit FIFO—General Operation:
When writing bytes to the XMTFIFO, certain restrictions
apply. These restrictions have a direct influence on the
latency provided by the FIFO to the host system. When
a byte is written to the FIFO location, the entire word lo-
cation is used. The unused byte is marked as a hole in
the XMTFIFO. These holes are skipped during the seri-
alization process performed by the MAC engine, when
the bytes are unloaded from the XMTFIFO.
For instance, assume the Transmit FIFO Watermark
(XMTFW) is set for 32 write cycles. If the host writes byte
wide data to the XMTFIFO, after 36 write cycles there
will be space left in the XMTFIFO for only 32 more write
cycles. Therefore TDTREQ will de-assert even though
only 36-bytes of data have been loaded into the
XMTFIFO. Transmission will not commence until
64-bytes or the End-of-Frame are available in the
XMFIFO, so transmission would not start, and TDTREQ
would remain de-asserted. Hence for byte wide data
transfers, the XMTFW should be programmed to the 8
or 16 write cycle limit, or the host should ensure that suf-
ficient data will be written to the XMTFIFO after
TDTREQ has been de-asserted (which is permitted), to
guarantee that the transmission will commence. A third
alternative is to program the Transmit Start Point
(XMTSP) in the BIU Configuration Control register to
below the 64-byte default; thereby imposing a lower la-
tency to the host system requiring additional data to
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