am79c940 Advanced Micro Devices, am79c940 Datasheet - Page 77

• Manufacturer Part Number: am79c940
• Description: Media Access Controller For Ethernet Mace
• Manufacturer: Advanced Micro Devices

Programmer’s Register Model (continued)
Addr
10
11
12
13
9
Mnemonic
FIFOCC
MACCC
BIUCC
IMR
PR
Interrupt Mask Register
80
40
20
10
08
04
02
01
Poll Register
80
40
20
Bus Interface Unit Configuration Control
80
40
30
01
FIFO Configuration Control
C0
30
08
04
02
01
Media Access Control (MAC) Configuration Control
80
40
20
10
08
04
02
01
JABM
BABLM
CERRM
RCVCCOM
RNTPCOM
MPCOM
RCVINTM
XMTINTM
XMTSV
TDTREQ
RDTREQ
—
BSWP
XMTSP—Transmit Start Point (2 bits)
00
01
10
11
SWRST
XMTFW
00
01
10
11
RCVFW
00
01
10
11
XMTFWU
RCVFWU
XMTBRST
RCVBRST
PROM
DXMT2PD
EMBA
—
DRCVPA
DRCVBC
ENXMT
ENRCV
Jabber Error Mask
Babble Error Mask
Collision Error Mask
Receive Collision Count Overflow Mask
Runt Packet Count Overflow Mask
Missed Packet Count Overflow Mask
Receive Interrupt Mask
Transmit Interrupt Mask
Transmit Status Valid
Transmit Data Transfer Request
Receive Data Transfer Request
Byte Swap
Transmit after 4 bytes have been loaded
Transmit after 16 bytes have been loaded
Transmit after 64 bytes have been loaded
Transmit after 112 bytes have been loaded
Software Reset
Transmit FIFO Watermark (2 bits)
Assert TDTREQ after 8 write cycles can be made
Assert TDTREQ after 16 write cycles can be made
Assert TDTREQ after 32 write cycles can be made
XX
Receive FIFO Watermark (2 bits)
Assert RDTREQ after 16 bytes are present
Assert RDTREQ after 32 bytes are present
Assert RDTREQ after 64 bytes are present
XX
Transmit FIFO Watermark Update—loads XMTFW bits
Receive FIFO Watermark Update—loads RCVFW bits
Select Transmit Burst mode
Select Receive Burst mode
Promiscuous mode
Disable Transmit Two Part Deferral
Enable Modified Back-off Algorithm
Disable Receive Physical Address
Disable Receive Broadcast
Enable Transmit
Enable Receive
Am79C940
Contents
AMD
R/W
R/W
R/W
R/W
R/W
RO
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