am79c940 Advanced Micro Devices, am79c940 Datasheet - Page 49

• Manufacturer Part Number: am79c940
• Description: Media Access Controller For Ethernet Mace
• Manufacturer: Advanced Micro Devices

Depending on the bus latency of the system, XMTFW
can be set to ensure that the Transmit FIFO does not
underflow before more data is written into the FIFO.
When the entire frame is in the FIFO, TDTREQ will re-
main asserted if sufficient bytes remain empty. The
default value of XMTFW is 64 bytes after hardware or
software reset. Note that if the XMTFW is set below the
64 byte limit, the transmit latency for the host to service
the MACE device is effectively increased, since
TDTREQ will occur earlier in the transmit sequence and
more bytes will be present in the Transmit FIFO when
the TDTREQ is de-asserted.
The transmit operation of the MACE device can be
halted at any time by clearing the ENXMT bit (bit 1) in the
MAC Configuration Control register. Note that any com-
plete transmit frame that is in the Transmit FIFO and is
currently in progress will complete, prior to the transmit
function halting. Transmit frames in the FIFO which
have not commenced will not be started. Transmit
frames which have commenced but which have not
been fully transferred into the Transmit FIFO will be
aborted, in one of two ways. If less than 544 bits
(68 bytes) have been transmitted onto the network, the
transmission will be terminated immediately, generating
a runt packet which can be deleted at the receiving sta-
tion. If greater than 544 bits have been transmitted, the
messages will have the current CRC inverted and ap-
pended at the next byte boundary, to guarantee an error
is detected at the receiving station. This feature ensures
that packets will not be generated with potential unde-
tected data corruption. An explanation of the 544 bit
The 544 bit count is derived from the following:
Minimum frame size (excluding preamble,
including FCS)
Preamble/SFD size
FCS size
To be classed as a minimum size frame at the receiver,
the transmitted frame must contain:
Preamble
1010....1010
+
Preamble
Bits
56
(Min Frame Size + FCS) bits
64 bytes
8 bytes
4 bytes
10101011
SFD
Bits
8
512 bits
64 bits
32bits
IEEE 802.3 Format Data Frame
Bytes
Addr
Dest
6
Am79C940
Bytes
Srce
Addr
derivation appears in the “ Automatic Pad Generation ”
section.
Automatic Pad Generation
Transmit frames can be automatically padded to extend
them to 64 data bytes (excluding preamble) permitting
the minimum frame size of 64 bytes (512 bits) for
802.3/Ethernet to be guaranteed, with no software inter-
vention from the host system.
APAD XMT = 1 enables the automatic padding feature.
The pad is placed between the LLC Data field and FCS
field in the 802.3 frame. The FCS is always added if
APAD XMT = 1, regardless of the state of DXMTFCS.
The transmit frame will be padded by bytes with the
value of 00h. The default value of APAD XMT will enable
auto pad generation after hardware or software reset.
It is the responsibility of upper layer software to correctly
define the actual length field contained in the message
to correspond to the total number of LLC Data bytes en-
capsulated in the packet (length field as defined in the
IEEE 802.3 standard). The length value contained in the
message is not used by the MACE device to compute
the actual number of pad bytes to be inserted. The
MACE chip will append pad bytes dependent on the ac-
tual number of bits transmitted onto the network. Once
the last data byte of the frame has completed, prior to
appending the FCS, the MACE device will check to en-
sure that 544 bits have been transmitted. If not, pad
bytes are added to extend the frame size to this value,
and the FCS is then added.
At the point that FCS is to be appended, the transmitted
frame should contain:
A minimum length transmit frame from the MACE
device will therefore be 576 bits, after the FCS is
appended.
The Ethernet specification makes no use of the LLC pad
field, and assumes that minimum length messages will
be at least 64 bytes in length.
6
Preamble
64
Length
Bytes
2
+
+
(Min Frame Size - FCS) bits
Data
LLC
46—1500
(512
Bytes
Pad
16235C-7
Bytes
-
FCS
4
32) bits
AMD
49