am79c940 Advanced Micro Devices, am79c940 Datasheet - Page 63

• Manufacturer Part Number: am79c940
• Description: Media Access Controller For Ethernet Mace
• Manufacturer: Advanced Micro Devices

Interrupt Mask Register (IMR)
This register contains the mask bits for the interrupts.
Read/write operations are permitted. Writing a one into
a bit will mask the corresponding interrupt. Writing a
zero to any previously set bit will unmask the corre-
sponding interrupt. Bit assignments for the register are
as follows:
Bit
Bit 7
Bit 6
Bit 5
Bit 4
RES
BABLM
JABM
BABLM
CERRM
RCVCCOM Receive Collision Count Over-
Name
CERRM RCVCCOM RNTPCOM
the transmission of a packet and
updated the Transmit Frame
Status. The INTR pin will be acti-
vated if the corresponding mask
bit XMTINTM = 0.
XMTINT is READ/CLEAR only. It
is set by the MACE device and
reset when read. Writing has no
effect. It is also cleared by activa-
tion of the RESET pin or SWRST
bit.
Description
Jabber Error Mask. JABM is the
mask for JAB. The INTR pin will
not be asserted by the MACE de-
vice regardless of the state of the
JAB bit, if JABM is set. It is
cleared by activation of the RE-
SET pin or SWRST bit.
Babble Error Mask. BABLM is
the mask for BABL. The INTR pin
will not be asserted by the MACE
device regardless of the state of
the BABL bit, if BABLM is set. It is
cleared by activation of the
RESET pin or SWRST bit.
Collision Error Mask. CERRM is
the mask for CERR. The INTR
pin will not be asserted by the
MACE device regardless of the
state of the CERR bit, if CERRM
is set. It is cleared by activation of
the RESET pin or SWRST bit.
flow Mask. RCVCCOM is the
mask for RCVCCO(Receive Col-
lision Count Overflow). The INTR
pin will not be asserted by the
MACE device regardless of the
state of the RCVCCO bit, if
RCVCCOM is set. It is cleared by
activation of the RESET pin or
SWRST bit.
MPCOM
(REG ADDR 9)
RCVINTM
XMTINTM
Am79C940
Bit 3
Bit 2
Bit 1
Bit 0
Poll Register (PR)
This register contains copies of internal status bits to
simplify a host implementation which is non-interrupt
driven. The register is read only, and its status is unaf-
fected by read operations. All register bits are cleared by
hardware or software reset. Bit assignments are as fol-
lows:
Bit
Bit 7
Bit 6
XMTSV
RNTPCOM Runt Packet Count Overflow
MPCOM
RCVINTM
XMTINTM
XMTSV
TDTREQ
TDTREQ RDTREQ
Name
Mask. RNTPCOM is the mask for
RNTPCO (Runt Packet Count
Overflow). The INTR pin will not
be asserted by the MACE device
regardless of the state of the
RNTPCO bit, if RNTPCOM is set.
It is cleared by activation of the
RESET pin or SWRST bit.
Missed Packet Count Overflow
Mask. MPCOM is the mask for
MPCO (Missed Packet Count
Overflow). The INTR pin will not
be asserted by the MACE device
regardless of the state of the
MPCO bit, if MPCOM is set. It is
cleared by activation of the
RESET pin or SWRST bit.
Receive
RCVINTM is the mask for
RCVINT. The INTR pin will not be
asserted by the MACE device re-
gardless of the state of the
RCVINT bit, if RCVINTM is set. It
is cleared by activation of the
RESET pin or SWRST bit.
Transmit
XMTINTM is the mask for
XMTINT. The INTR pin will not be
asserted by the MACE device re-
gardless of the state of the
XMTINT bit, if XMTINT is set. It is
cleared by activation of the RE-
SET pin or SWRST bit.
Description
Transmit Status Valid. Transmit
Status Valid indicates that the
Transmit Frame Status is valid.
Transmit Data Transfer Request.
An internal indication of the cur-
rent request status of the Trans-
mit FIFO. TDTREQ is set when
the external TDTREQ signal is
asserted.
RES
RES
Interrupt
Interrupt
(REG ADDR 10)
RES
RES
AMD
Mask.
Mask.
RES
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