am79c930 Advanced Micro Devices, am79c930 Datasheet - Page 38

• Manufacturer Part Number: am79c930
• Description: Pcnet-mobile Single-chip Wireless Lan Media Access Controller
• Manufacturer: Advanced Micro Devices

Pin 101: SDCLK
The SDCLK pin may be configured for input or output
operation. The output drive may be programmed for reg-
ister-driven or auto-pulse generation. The auto-pulse
may be programmed for either active low or active high
Pin 102: SDDATA
The SDDATA pin may be configured for input or output
operation. SDDATA pin configuration is accomplished
according to the following table:
Pin 103: SDSEL3
The SDSEL[3] pin may be configured for input or output
operation according to the following table:
Pin 105: SDSEL2
The SDSEL[2] pin may be configured for input or output
operation according to the following table:
Pin 107: SDSEL1
The SDSEL[1] pin may be configured for input or output
operation according to the following table:
38
SDCLKEN
TCR13[4]
SDSEL3EN
SDSEL2EN
SDSEL1EN
AMD
TCR13[3]
TCR13[2]
TCR13[1]
TIR2[1]
0
1
1
1
1
SDDT
0
0
1
0
1
1
0
1
1
0
1
1
TIR2[3]
SDCP
X
0
1
0
1
TIR2[0]
SDS[3]
TIR2[6]
SDS[2]
TIR2[5]
SDS[1]
TIR2[4]
SDD
X
X
X
X
0
1
0
1
0
1
0
1
TIR2[2]
SDC
X
0
0
1
1
Pin Direction
Pin Direction
Pin Direction
SDDATA Pin
SDSEL[3]
SDSEL[2]
SDSEL[1]
Direction
SDCLK Pin
Direction
P R E L I M I N A R Y
O
O
O
O
O
O
O
O
I
I
I
I
O
O
O
O
I
Am79C930
HIGH active pulse
LOW active pulse
operation. SDCLK pin configuration is accomplished ac-
cording to the following table:
Note that a read of the SDC bit (TIR2[2]) will always
give the current SDCLK pin value, regardless of pin
configuration setting.
Note that a read of the SDD bit (TIR2[0]) will always
give the current SDDATA pin value, regardless of pin
configuration setting.
Note that a read of the SDS[3] bit (TIR2[6]) will always
give the current SDSEL[3] pin value without inversion,
regardless of pin configuration setting.
Note that a read of the SDS[2] bit (TIR2[5]) will always
give the current SDSEL[2] pin value without inversion,
regardless of pin configuration setting.
Note that a read of the SDS[1] bit (TIR2[4]) will always
give the current SDSEL[1] pin value without inversion,
regardless of pin configuration setting.
SDCLK Pin
SDDATA Pin
SDSEL[3]
Pin Value
SDSEL[2]
Pin Value
SDSEL[1]
Pin Value
Value
HIGH
LOW
NA
Value
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
NA
NA
NA
NA
reset default condition
(when write to TIR2 occurs)
(when write to TIR2 occurs)
reset default condition
reset default condition
reset default condition
reset default condition