am79c930 Advanced Micro Devices, am79c930 Datasheet - Page 49

• Manufacturer Part Number: am79c930
• Description: Pcnet-mobile Single-chip Wireless Lan Media Access Controller
• Manufacturer: Advanced Micro Devices

The values HDR, DRB, TGAP1, TGAP2, TGAP3, and
TGAP4 are programmable values that are stored in
TCR register locations TCR0, TCR5, and TCR6. All
other timings in the diagram are fixed with the values in-
dicated. The CLKGT20 control bit is located in MIR9[7].
The timing of the five internal signals can be applied to
the external pins TXCMD, TXPE, and TXMOD in
either of two ways, depending upon the value pro-
grammed into the RCEN bit of TIR11 as shown in the
following table:
Pin
Name
TXCMD
TXPE
TXMOD
TXP_ON
TXDATA
O_TX
Timing Reference
TXS
When RCEN=0
T1
T2
T3
TXP_ON
O_TX
T3
TSCLK = TCLKIN when
CLKGT20 = 0
TBCLK = TSCLK X 20
TX default bit
4 X TSCLK
Timing Reference
Figure 1. Transmitter Power Ramp Control
When RCEN=1
HDB X TBCLK
TGAP1 X TBCLK
T1
T2
T3
TGAP2 X TBCLK
+ 2 X TSCLK
P R E L I M I N A R Y
+ 2 X TSCLK
2 X TSCLK
Am79C930
3 X TSCLK
Note that the TXCMD, TXPE, and TXMOD bits of TIR11
may also affect the values of the TXCMD, TXPE, and
TXMOD pins. See the individual descriptions of these
pins in the Multi-Function Pin section of this document
for more detail.
The polarity of TXMOD and TXPE are programmable. A
separate TXCMD signal (inverse polarity to TXCMD)
is available.
Data Bit
1st
TGAP3 X TBCLK
Data Bit
2 X TSCLK
Last
+ 2 X TSCLK
TGAP4 X TBCLK
+ 2 X TSCLK
DRB X TBCLK
7 X TSCLK
TX default bit
20183B-7
AMD
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