am79c30a Advanced Micro Devices, am79c30a Datasheet - Page 10

• Manufacturer Part Number: am79c30a
• Description: Digital Subscriber Controller ?dsc ?circuit
• Manufacturer: Advanced Micro Devices

INIT2 Register (INIT2) default = 00H
Address = Indirect 20 Hex, Read/Write
A special write procedure must be followed in order to
modify the contents of the INIT2 Register, since the
INIT2 Register includes control bits which could result
in the stopping of the microprocessor clock. This proce-
dure greatly reduces the probability of errant software
disabling the system, and is described as follows:
1. Write the INIT2 address to the Command Register.
2. Write to the Data Register (INIT2 is not yet up-
3. Write the INIT2 address to the Command Register.
4. Write to the Data Register (INIT2 is updated).
The writes must take place without any intervening in-
direct accesses to the DSC/IDC circuit.
10
7 6 5 4 3 2 1 0 Function
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
dated).
X X X X X X Reserved, must be written to 0;
X 0 X X X X Multiframe Interrupt filter
X 1 X X X X Multiframe Interrupt filter
X X X 0 X X Clock speed-up option disabled
X X X 1 X X Clock speed-up option enabled;
X X X 0 0 0 MCLK frequency determined by
X X X 0 0 1 MCLK frequency is 1.536 MHz
X X X 0 1 0 MCLK frequency is 768 kHz
X X X 0 1 1 MCLK frequency is 384 kHz
X X X 1 0 0 MCLK stopped in High state
X X X 1 0 1 Reserved
X X X 1 1 0 Reserved
X X X 1 1 1 Reserved
0 X X X X X Power-Down disabled; writing
1 X X X X X Power-Down enabled; writing
Bit
Table 2. INIT2 Register
READs are undefined
11 to the INIT Register will put
the DSC/IDC circuit into Idle
mode
11 to the INIT Register will put
the DSC/IDC circuit into
Power-Down mode
disabled
enabled (see LIU section for
detailed description)
if set, this register bit will be
cleared when the DLC FIFO
receive threshold or second
packet received interrupt is
triggered
INIT Register
Am79C30A/32A Data Sheet
RESET Operation
The Am79C30A/32A can be reset by driving the
RESET pin High. When power is first supplied to the
DSC/IDC circuit, a reset must be performed. This ini-
tializes the DSC/IDC circuit to its default condition as
defined in Table 3.
Receive and Transmit Abort Commands
The microprocessor has the option via INIT Register
bits 6 and 7 to abort the receive and transmit D-channel
packets. When the microprocessor sets one of these
bits, the Am79C30A/32A aborts the respective opera-
tion. The frame abort sequence is defined in greater
detail later. (See the Data Link Controller section on
page 36.)
Interrupt Handling
The Am79C30A/32A generates either no interrupt or
only one interrupt every 125 µs. Once asserted, INT re-
mains active until the microprocessor responds by inter-
rogating the Am79C30A/32A’s Interrupt Register (IR)
(see Table 4). Reading the IR in response to an acti-
vated INT pin deactivates the INT pin and clears the IR.
If an event causing an interrupt occurs while the IR is
being read by the microprocessor, the effect of the
event is held until the microprocessor has completed its
read cycle. A reset clears all conditions causing inter-
rupts.
Bits 0, 1, and 4 of the IR, if set, advise the microproces-
sor that the respective buffer is ready for reading or
writing. If bit 0 is set due to an empty buffer, the D-chan-
nel Transmit buffer must be serviced within 375 s. If bit
1 is set and the D-channel Receive buffer is full, the
buffer must be serviced within 425 s. This is to prevent
erroneous data transfers causing transmitter underrun
and receiver overrun errors. If bit 4 is set then the Bb or
Pin Name
D7–D0
MCLK
INT
SBOUT
SFS
SCLK
LS1, LS2
EAR1
EAR2
AREF
LOUT1
LOUT2
Table 3. Reset Pin Conditions
State Following RESET
High Impedance
6.144 MHz
Logical 1
High Impedance
High Impedance
High Impedance
High Impedance
High Impedance
High Impedance
High Impedance
High Impedance
High Impedance