am79c30a Advanced Micro Devices, am79c30a Datasheet - Page 63

• Manufacturer Part Number: am79c30a
• Description: Digital Subscriber Controller ?dsc ?circuit
• Manufacturer: Advanced Micro Devices

C/I Transmit Data Register 0 (C/ITDR0) Default = 0F Hex
Address = Indirect C4 Hex, Write
The C/I Transmit Data Register 0 is the user-visible portion of the C/I channel 0 transmitter. Data can be written into
this register by the user at any time and is transmitted continuously during each subsequent frame until changed.The
register is set to its default value, 0F hex (C/I channel idle), by reset or disabling of the Peripheral Port. Bus access
request bit-When set, the DSC will attempt to gain access to the C/I0 channel if TIC bus is enabled.
C/I Receive Data Register 0 (C/IRDR0) Default = XF Hex
Address = Indirect C4 Hex, Read
The C/I Receive Data Register 0 contains data valid for two frames from C/I Receive channel 0. The register is set
to its default value of XF hex by a reset or the disabling of the Peripheral Port.
C/I Transmit Data Register 1 (C/ITDR1) Default = 3F Hex
Address = Indirect C5 Hex, Write
The C/I Transmit Data Register 1 is the user-visible portion of the C/I channel 1 transmitter. Data can be written into
this register by the user at any time. It is transmitted continuously during each subsequent frame until changed. The
register is set to its default value, 3F hex (C/I channel idle), by reset or disabling of the Peripheral Port.
C/I Receive Data Register 1 (C/IRDR1)
Default = Bits 7 and 6 are Indeterminate, Bits 5–0 = 1
Address = Indirect C5 Hex, Read
The C/I Receive Data Register 1 contains the data (valid for two frames) from C/I Receive channel 1. The register
is set to its default value by a reset or the disabling of the Peripheral Port.
Bus Access
Request
RSRVD
RSRVD
RSRVD
7
7
7
7
RSRVD
RSRVD
RSRVD
RSRVD
6
6
6
6
RSRVD
RSRVD
(MSB)
(MSB)
DATA
BIT 5
DATA
BIT 5
C/I1
C/I1
5
5
5
5
Am79C30A/32A Data Sheet
RSRVD
RSRVD
DATA
BIT 4
DATA
BIT 4
C/I1
C/I
4
4
4
4
(MSB)
(MSB)
DATA
BIT 3
DATA
BIT 3
DATA
BIT 3
DATA
BIT 3
C/I0
C/I0
C/I1
C/I1
3
3
3
3
DATA
BIT 2
DATA
BIT 2
DATA
BIT 2
DATA
BIT 2
C/I0
C/I0
C/I1
C/I1
2
2
2
2
DATA
BIT 1
DATA
BIT 1
DATA
BIT 1
DATA
BIT 1
C/I0
C/I0
C/I1
C/I1
1
1
1
1
(LSB)
(LSB)
(LSB)
(LSB)
DATA
BIT 0
DATA
DATA
BIT 0
DATA
BIT 0
BIT0
C/I0
C/I0
C/I1
C/I1
0
0
0
0
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