am79c30a Advanced Micro Devices, am79c30a Datasheet - Page 21

• Manufacturer Part Number: am79c30a
• Description: Digital Subscriber Controller ?dsc ?circuit
• Manufacturer: Advanced Micro Devices

Multiframe S-bit/Status Buffer (MFSB), Read Only
Address = Indirect A7H
The MFSB reset default value is 40H.
Multiframe Q-bit Buffer (MFQB), Write Only
Address = Indirect A8H
Multiplexer (MUX)
The MUX contains the registers found in Table 17.
The Multiplexer is used to selectively route 64-Kbit/s
full-duplex B channels between the LIU (Line Interface
Unit), MAP (Main Audio Processor), MPI (Microproces-
sor Interface), and the PP (Peripheral Port).
Register
MUX Control
Registers
Bit
0
1
2
3
4
5
6
7
5, 6, 7
Bit
0
1
2
3
4
Table 15. Multiframe S-Bit/Status Buffer
Description
S1
S2
S3
S4
S5
S-data available
Q-bit buffer empty
Multiframe change of state If MF bit 3 = 1
Table 16. Multiframe Q-Bit Buffer
Description
Q1 (default = 1)
Q2 (default = 1)
Q3 (default = 1)
Q4 (default = 1)
Q-bit value when multiframing enabled but
synchronization not achieved (default = 0)
Not used
Table 17. MUX Registers
No./Registers
4
Mnemonic
MCR1, MCR2, MCR3,
MCR4
If MF bit 2 = 1
Generates Interrupt
No
No
No
No
No
If MF bit 1 = 1
Am79C30A/32A Data Sheet
The logical channels available at the MUX are shown in
Figure 2, They are:
1. From/to the LIU channels B1 and B2
2. From/to the MAP channel Ba
3. From/to the MPI channels Bb and Bc
4. From/to the PP channels Bd, Be, and Bf
For any specific application, the MUX can be pro-
grammed by the microprocessor to route any three
B- ch an n el p or ts to a ny o the r thr ee B- ch a nn e l
ports.Programmable bidirectional bit reversal is pro-
vided for both of the MPI data channels Bb and Bc.
MUX Control Registers 1, 2, and 3
(MCR1, MCR2, and MCR3), Read/Write
Addresses = Indirect 41H, 42H, 43H
The MUX can support three bidirectional paths. The
contents of the MUX Control Registers MCR1, MCR2,
and MCR3 direct the flow of data between the eight
MUX logical B channels (see Figure 2). These three
MCRs are programmed to connect any two B-channel
ports together by writing the appropriate channel code
into an MCR. These MCRs have the same format,
where bits 7–4 indicate port 1 and bits 3–0 indicate port
2. In each of these three MCR registers, the channel
codes found in Table 18 are used for both ports 1 and 2.
For example, to connect B1(LIU) with Bb (MPI) and B2 (LIU)
with Ba (MAP), the contents of the MCRs would be:
Register 7 6 5 4 3 2 1 0 Channel Connection
Code
0000
0001
0010
0011
0100
0101
0110
0111
1000
MCR1
MCR2
MCR3
Table 18. MCR Register Channel Codes
0 0 0 1 0 1 0 0 B1 (LIU)
0 0 1 0 0 0 1 1 B2 (LIU)
0 0 0 0 0 0 0 0 No connect
Port 1
No connection (default value)
B1 (LIU)
B2 (LIU)
Channel
Ba (MAP)
Bb (MPI)
Bc (MPI)
Bd (PP channel 1)
Be (PP channel 2)
Bf (PP channel 3)
Port 2
No connect
Ba (MAP)
Bb (MPI)
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