am79c30a Advanced Micro Devices, am79c30a Datasheet - Page 16

• Manufacturer Part Number: am79c30a
• Description: Digital Subscriber Controller ?dsc ?circuit
• Manufacturer: Advanced Micro Devices

point-to-multipoint configuration can have multiple TEs
connected to one NT.
Line Code
Pseudo-ternary coding is used for both transmitting
and receiving over the S Interface. In this type of cod-
ing, a binary 1 is represented by a space (zero voltage),
and a binary 0 is represented by a High mark or a Low
mark. Two consecutive binary 0s are represented by al-
ternate marks to reduce DC offset on the line. A mark
followed, either immediately or separated by spaces,
by a mark of the same polarity, is defined as a code vi-
olation. Code violations are used to identify the bound-
aries of the frame.
Note:
The DSC defines “Any Signal” as any frame with at least
three marks above receive threshold.
Frame Structures
In both transmit and receive directions, the bits are
grouped into frames of 48 bits each. The frame struc-
ture is identical for both point-to-point and point-to-mul-
tipoint configurations. Each frame transmitted at 4 kHz
consists of several groups of bits.
Multiframing
If multiframing is enabled, the Am79C30A/32A recog-
nizes and establishes multiframe synchronization
based on the monitoring of the F
(M-bit control) bits. The Am79C30A/32A also receives
and compiles S bits, and transmits Q bits synchronized
to the received frame.
Establishment of Multiframe Synchronization
When the enable multiframe synchronization bit (bit 0
of the Multiframe Register) is set and the LIU is in either
state F6 or F7, the LIU monitors the F
and M (M-bit control) bits. When three consecutive mul-
tiframes with the M bits and F
Table 8 are received, the multiframe synchronized bit
16
MUX
DLC
and
To
Decoder
A
A
bits set as defined in
(Q-bit control) and M
A
(Q-bit control)
Figure 1. LIU Block Diagram
Am79C30A/32A Data Sheet
Recovery
Frame
Slicer
Pseudo-ternary
(bit 7 of the Multiframe Register) and multiframe
change of state bit (bit 7 of the Multiframe S bit/Status
buffer) are set. Note that S-bit data is received, com-
piled, and transferred to the user after attaining syn-
chronization at the start of the next multiframe.
S-Bit Reception
The default operation of the DSC/IDC circuit is that the
LIU will receive and pass multiframe data to the user in
5-bit increments four times per multiframe, regardless
of the value of the data. After multiframe synchroniza-
tion has been requested and established the micropro-
cessor can read the Multiframe S bit/Status buffer
(MFSB) once the S-bit available bit (MFSB bit 5) is set.
The S-data available bit is set to a logical 1 when the
Am79C30A/32A has received five S bits (one S bit per
S-interface frame) synchronized to the setting of the
F
MFSB. Once the S-bit available bit is set, the MFSB
must be accessed within 1.25 ms or succeeding S data
will be lost.
Subsequent to the original definition of the DSC/IDC
circuit, the CCITT has defined a structure for the 20
multiframe bits, which specifies five 4-bit channels. Fur-
thermore, the idle code for these channels has been
defined as 0000. An enhanced mode of multiframe re-
ception has been included, which may be enabled by
setting INIT2 bit 4 to a 1. This enhanced mode reduces
processor overhead by generating an interrupt only
upon the reception of a non-zero S-channel word.
INIT2 bit 4 will be automatically cleared by hardware
when the five received data bits in the MFSB are not all
0s, as long as MF bit 1 (interrupt enable) is set. This al-
lows subsequent valid all-zero words to be received.
Furthermore, when the first five S bits of the multiframe
are loaded into the MFSB, bit 4 of the MF register will
be set, which allows identification of the position of re-
ceived words within the multiframe.
A
-bit to a logical 1 and transferred them into the
Recovery
Binary
Timing
Coder
to
Balanced
Line Drivers
Receiver
09893H-2
S